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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-25 02:50:43 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 16:19:46 +0000 |
| commit | 52742b6dbd22203a919fb7555953e2839e6e776f (patch) | |
| tree | 21c546e135e3882e3ad3dff877ec6d3b5585e904 /src/soc/amd/mendocino/chipset_mendocino.cb | |
| parent | e91392a5fe28eeb23e1791de15c31c3f5c8a6a82 (diff) | |
soc/amd/common/acpi/cpu_power_state: introduce and use get_pstate_0_reg
On the Zen-based CPUs, P state 0 corresponds to the first P state MSR,
but on Stoneyridge this isn't the case. Introduce get_pstate_0_reg that
returns 0 for all non-CAR AMD CPUs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icc11e5b6099d37edb934e66fe329d8013d25f68d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/mendocino/chipset_mendocino.cb')
0 files changed, 0 insertions, 0 deletions