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authorSubrata Banik <subratabanik@google.com>2023-01-16 13:52:40 +0530
committerFelix Held <felix-coreboot@felixheld.de>2023-01-17 19:25:35 +0000
commitd4cc902c57ca6e57ebf27e8fc63748f984a1d868 (patch)
tree1ad876d596a506c4215c9ecd90d89b9852322333 /src/soc/amd/mendocino/acpi.c
parent55812d6430b3bcab3961943621fe2784a3e2b79a (diff)
soc/intel/meteorlake: Avoid redundant chipset programming in romstage
This patch refactors the mainboard_romstage_entry() function to avoid redundant chipset programming caused by global reset due to CSE FW sync operation. Hence, keeping only the minimal and mandatory operations required to perform CSE FW sync successfully. This would help to optimize the boot flow by removing redundant programming like SA, SMBUS twice in every CSE FW update path. TEST=Able to build and boot Google/Rex successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1a13fac1e99341991d8dd818d4ab8a20d209a94c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71933 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/mendocino/acpi.c')
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