diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-08-24 15:12:19 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-31 10:36:39 +0000 |
| commit | 7fcd4d58ec7ea2da31c258ba9d8601f086d7f8d8 (patch) | |
| tree | 1bddf10cecf4577fee207e0dbc6f7a5c1b10af13 /src/soc/amd/genoa_poc | |
| parent | 3138faa7cf1b91e0b56ad0b1be6260cf4251a284 (diff) | |
device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/genoa_poc')
| -rw-r--r-- | src/soc/amd/genoa_poc/domain.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index dc3745061d..57e020a4b4 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -18,7 +18,7 @@ static void genoa_domain_read_resources(struct device *domain) amd_pci_domain_read_resources(domain); // We only want to add the DRAM memory map once - if (domain->link_list->secondary == 0 && domain->link_list->segment_group == 0) { + if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) { /* 0x1000 is a large enough first index to be sure to not overlap with the resources added by amd_pci_domain_read_resources */ add_opensil_memmap(domain, 0x1000); @@ -27,7 +27,7 @@ static void genoa_domain_read_resources(struct device *domain) static void genoa_domain_set_resources(struct device *domain) { - if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n", domain->path.domain.domain); const union df_vga_en vga_en = { |