soc/amd/genoa: rename to genoa_poc

Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.

Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 31 insertions, 0 deletions

diff --git a/src/soc/amd/genoa_poc/mmap_boot.c b/src/soc/amd/genoa_poc/mmap_boot.c
new file mode 100644
index 0000000000..d29af41636
--- /dev/null
+++ b/src/soc/amd/genoa_poc/mmap_boot.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot_device.h>
+#include <endian.h>
+#include <spi_flash.h>
+
+#if CONFIG_ROM_SIZE >= (16 * MiB)
+#define ROM_SIZE (16 * MiB)
+#else
+#define ROM_SIZE CONFIG_ROM_SIZE
+#endif
+
+/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */
+#define rom_base ((void *)(uintptr_t)(0x100000000ULL-ROM_SIZE))
+
+static const struct mem_region_device boot_dev =
+	MEM_REGION_DEV_RO_INIT(rom_base, ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+	return &boot_dev.rdev;
+}
+
+uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table)
+{
+	table->flash_base = 0;
+	table->host_base = (uint32_t)(uintptr_t)rom_base;
+	table->size = ROM_SIZE;
+
+	return 1;
+}