diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-12-15 10:57:30 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-16 20:14:34 +0000 |
| commit | d123f8d8716811149ecdf7d51661d8cee6f48577 (patch) | |
| tree | 36c6ae14a65508adac7889c4d43fa098db0bafca /src/soc/amd/genoa_poc/fw.cfg | |
| parent | 1c295092d61c2ac7427ddac6d194d99337f86094 (diff) | |
soc/amd/genoa: rename to genoa_poc
Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.
Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/genoa_poc/fw.cfg')
| -rw-r--r-- | src/soc/amd/genoa_poc/fw.cfg | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/soc/amd/genoa_poc/fw.cfg b/src/soc/amd/genoa_poc/fw.cfg new file mode 100644 index 0000000000..d8297fda36 --- /dev/null +++ b/src/soc/amd/genoa_poc/fw.cfg @@ -0,0 +1,54 @@ +# PSP fw config file +FIRMWARE_LOCATION 3rdparty/amd_blobs/genoa/PSP +SOC_NAME Genoa + +# type file +# PSP +AMD_PUBKEY_FILE Typex0_0_0_0_AmdPubKey.bin +PSPBTLDR_FILE Typex1_0_0_0_PspBootLoader.bin Lbb +PSPRCVR_FILE Typex3_0_0_0_PspRecBL.bin +PSP_SMUFW1_SUB0_FILE Typex8_0_0_0_Smu.bin +PSP_SMUFW1_SUB1_FILE Typex8_0_0_1_Smu.bin +PSP_SMUFW1_SUB2_FILE Typex8_0_0_2_Smu.bin +PSPSECUREDEBUG_FILE Typex9_0_0_0_DbgKey.bin +PSP_OEM_ABL_KEY_FILE Typexa_0_0_0_OemAblKey.bin +PSP_SMUFW2_SUB0_FILE Typex12_0_0_0_Smu2.bin +PSP_SMUFW2_SUB1_FILE Typex12_0_0_1_Smu2.bin +PSP_SMUFW2_SUB2_FILE Typex12_0_0_2_Smu2.bin Lbb +PSP_SEC_DEBUG_FILE Typex13_0_0_0_PspEarlyUnlock.bin Lbb +PSP_IKEK_FILE Typex21_0_0_0_ikek.bin +PSP_TOKEN_UNLOCK_FILE Typex22_0_0_0_PspTokenUnlockData.bin +PSP_SECG0_FILE Typex24_0_0_0_SecureGasket.bin +PSP_SECG1_FILE Typex24_0_0_1_SecureGasket.bin +PSP_SECG2_FILE Typex24_0_0_2_SecureGasket.bin +PSP_MP5FW_SUB0_FILE Typex2a_0_0_0_Mp5Fw.bin +PSP_MP5FW_SUB1_FILE Typex2a_0_0_1_Mp5Fw.bin +PSP_MP5FW_SUB2_FILE Typex2a_0_0_2_Mp5Fw.bin +PSP_ABL0_FILE Typex30_0_0_0_PspAgesaBL0.bin +SEV_CODE_FILE Typex39_0_0_0_SevCode.bin +SEV_DATA_FILE Typex38_0_0_0_SevData.bin +PSP_DXIOFW_FILE Typex42_0_0_0_DxioFw.bin +UNIFIEDUSB_FILE Typex44_0_0_0_UsbPhyFw.bin +DRTMTA_FILE Typex47_0_0_0_DrtmTa.bin +KEYDBBL_FILE Typex50_0_0_0_PspBlPubKey.bin +SPL_TABLE_FILE Typex55_0_0_0_BLAntiRB.bin Lbb +PSP_MPIOFW_FILE Typex5d_0_0_0_MPIOOffchipFW.bin +PSP_RIB_FILE_SUB0 Typex76_0_0_0_RIB.bin +PSP_MPDMATFFW_FILE Typex8c_0_0_0_MpdmaTfFw.bin +PSP_GMI3PHYFW_FILE Typex91_0_0_0_Gmi3PhyFw.bin +PSP_MPDMAPMFW_FILE Typex92_0_0_0_MpdmaPmFw.bin +AMD_FUSE_CHAIN Dummy Lbb + +# BDT +PSP_PMUI_FILE_SUB0_INS3 Typex64_0_3_0_PmuCode.bin +PSP_PMUI_FILE_SUB0_INS4 Typex64_0_4_0_PmuCode.bin +PSP_PMUI_FILE_SUB0_INS9 Typex64_0_9_0_PmuCode.bin +PSP_PMUI_FILE_SUB0_INSA Typex64_0_a_0_PmuCode.bin +PSP_PMUI_FILE_SUB0_INSB Typex64_0_b_0_PmuCode.bin +PSP_PMUD_FILE_SUB0_INS3 Typex65_0_3_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INS4 Typex65_0_4_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INS9 Typex65_0_9_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INSA Typex65_0_a_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INSB Typex65_0_b_0_PmuData.bin +PSP_PMUD_FILE_SUB0_INSC Typex65_0_c_0_PmuData.bin +# TODO: Typex69_0_0_0_EarlyVgaImage.bin |