soc/amd/genoa: rename to genoa_poc

Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.

Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 94 insertions, 0 deletions

diff --git a/src/soc/amd/genoa_poc/fch.c b/src/soc/amd/genoa_poc/fch.c
new file mode 100644
index 0000000000..c9779571da
--- /dev/null
+++ b/src/soc/amd/genoa_poc/fch.c
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpi.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/amd_pci_util.h>
+#include <amdblocks/gpio.h>
+#include <amdblocks/smi.h>
+#include <bootstate.h>
+#include <cpu/x86/smm.h>
+#include <soc/acpi.h>
+#include <soc/amd_pci_int_defs.h>
+#include <soc/smi.h>
+#include <soc/southbridge.h>
+
+/*
+ * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
+ * provides a visible association with the index, therefore helping
+ * maintainability of table. If a new index/name is defined in
+ * amd_pci_int_defs.h, just add the pair at the end of this table.
+ * Order is not important.
+ */
+static const struct irq_idx_name irq_association[] = {
+	{ PIRQ_A,	"INTA#" },
+	{ PIRQ_B,	"INTB#" },
+	{ PIRQ_C,	"INTC#" },
+	{ PIRQ_D,	"INTD#" },
+	{ PIRQ_E,	"INTE#" },
+	{ PIRQ_F,	"INTF#/GENINT2" },
+	{ PIRQ_G,	"INTG#" },
+	{ PIRQ_H,	"INTH#" },
+	{ PIRQ_MISC,	"Misc" },
+	{ PIRQ_MISC0,	"Misc0" },
+	{ PIRQ_HPET_L,	"HPET_L" },
+	{ PIRQ_HPET_H,	"HPET_H" },
+	{ PIRQ_SIRQA,	"Ser IRQ INTA" },
+	{ PIRQ_SIRQB,	"Ser IRQ INTB" },
+	{ PIRQ_SIRQC,	"Ser IRQ INTC" },
+	{ PIRQ_SIRQD,	"Ser IRQ INTD" },
+	{ PIRQ_SCI,	"SCI" },
+	{ PIRQ_SMBUS,	"SMBUS" },
+	{ PIRQ_ASF,	"ASF" },
+	{ PIRQ_PMON,	"PerMon" },
+	{ PIRQ_SDIO,	"SDIO" },
+	{ PIRQ_GPP0,	"GPP0" },
+	{ PIRQ_GPP1,	"GPP1" },
+	{ PIRQ_GPP2,	"GPP2" },
+	{ PIRQ_GPP3,	"GPP3" },
+	{ PIRQ_GSCI,	"GEvent SCI" },
+	{ PIRQ_GSMI,	"GEvent SMI" },
+	{ PIRQ_GPIO,	"GPIO" },
+	{ PIRQ_I2C0,	"I2C0" },
+	{ PIRQ_I2C1,	"I2C1" },
+	{ PIRQ_I2C2,	"I2C2" },
+	{ PIRQ_I2C3,	"I2C3" },
+	{ PIRQ_UART0,	"UART0" },
+	{ PIRQ_UART1,	"UART1" },
+	{ PIRQ_I2C4,	"I2C4" },
+	{ PIRQ_I2C5,	"I2C5" },
+	{ PIRQ_UART2,	"UART2" },
+	{ PIRQ_UART3,	"UART3" },
+};
+
+const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
+{
+	*size = ARRAY_SIZE(irq_association);
+	return irq_association;
+}
+
+static void set_pci_irqs(void)
+{
+	/* Write PCI_INTR regs 0xC00/0xC01 */
+	write_pci_int_table();
+
+	/* TODO: PIRQ configuration */
+}
+
+static void fch_init_acpi_ports(void)
+{
+	/* Configure and enable APMC SMI Command Port */
+	pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
+	configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+}
+
+static void fch_init(void *unused)
+{
+	set_pci_irqs();
+	fch_init_acpi_ports();
+}
+
+/*
+ * Hook this function into the PCI state machine on entry into BS_DEV_ENABLE.
+ * TODO: can this be done without using BOOT_STATE_INIT_ENTRY?
+ */
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fch_init, NULL);