diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-14 23:05:46 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 15:16:23 +0000 |
commit | 447e27937ca38a9e10a705b0770b71fca7cf4712 (patch) | |
tree | 9e9acc5922f613109b323a325da4eb5e5ed87749 /src/soc/amd/genoa/mca.c | |
parent | 2e2f1661bb306d7b00b4f121148e9613c5d14e72 (diff) |
soc/amd/genoa: Hook up MCA code
This patch uses AMD SoC common code for MCA and adds MCA bank
information as per Genoa Processor Programming Reference (PPR)
version 0.25 (#55901) and uses AMD SoC common code.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If728d803d600f7e86507cd1b35b40022bf4d379e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76524
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/genoa/mca.c')
-rw-r--r-- | src/soc/amd/genoa/mca.c | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/mca.c b/src/soc/amd/genoa/mca.c new file mode 100644 index 0000000000..9a6df2b53e --- /dev/null +++ b/src/soc/amd/genoa/mca.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <cpu/x86/msr.h> +#include <types.h> + +/* TODO: Check if non-core MCA banks are same for all cores */ +static const char *const mca_bank_name[] = { + [0] = "Load-store unit", + [1] = "Instruction fetch unit", + [2] = "L2 cache unit", + [3] = "Decode unit", + [4] = "", + [5] = "Execution unit", + [6] = "Floating point unit", + [7] = "L3 cache unit", + [8] = "L3 cache unit", + [9] = "L3 cache unit", + [10] = "L3 cache unit", + [11] = "L3 cache unit", + [12] = "L3 cache unit", + [13] = "L3 cache unit", + [14] = "L3 cache unit", + [15] = "Microprocessor5 Management Controller", + [16] = "Parameter Block", + [17] = "GMI Controller", + [18] = "GMI Controller", + [19] = "High Speed Interface Unit (GMI)", + [20] = "High Speed Interface Unit (GMI)", + [21] = "Unified Memory Controller", + [22] = "Unified Memory Controller", + [23] = "Coherent Station", + [24] = "Coherent Station", + [25] = "Northbridge IO Unit", + [26] = "PCIe Root Port", + [27] = "PCIe Root Port", + [28] = "Power Management, Interrupts, Etc.", + [29] = "SMU", + [30] = "XGMI Controller", + [31] = "High Speed Interface Unit (XGMI)", +}; + +bool mca_has_expected_bank_count(void) +{ + return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); +} + +bool mca_is_valid_bank(unsigned int bank) +{ + return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); +} + +const char *mca_get_bank_name(unsigned int bank) +{ + if (mca_is_valid_bank(bank)) + return mca_bank_name[bank]; + else + return ""; +} |