diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-10-13 21:19:53 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-27 12:34:23 +0000 |
| commit | 926887ced904faeda461b923761bed441cde0acc (patch) | |
| tree | 043668dff926cc7caac35f9f091bfc3e8759a2b4 /src/soc/amd/genoa/chipset.cb | |
| parent | 0f209b58d2e0d884b4ce9e76e0a769d122e99ac8 (diff) | |
soc/amd/genoa: add PCI domain resource reporting
Use the common AMD data fabric resource reporting code to report how
openSIL distributed PCI buses, MMIO, and IO resources to coreboot's
resource allocator. This replaces the original CB:76521 which was
written back when the common AMD data fabric resource reporting code
didn't exist yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ifcd655ea6d5565668ffee36d0d022b2b711c0b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/soc/amd/genoa/chipset.cb')
| -rw-r--r-- | src/soc/amd/genoa/chipset.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb index 6fd6bf3002..45eeec78ba 100644 --- a/src/soc/amd/genoa/chipset.cb +++ b/src/soc/amd/genoa/chipset.cb @@ -5,6 +5,7 @@ chip soc/amd/genoa end device domain 0 on + ops genoa_pci_domain_ops device pci 00.0 alias gnb_0 on end device pci 00.2 alias iommu_0 on ops amd_iommu_ops end device pci 00.3 alias rcec_0 off end @@ -72,6 +73,7 @@ chip soc/amd/genoa end device domain 1 on + ops genoa_pci_domain_ops device pci 00.0 alias gnb_1 on end device pci 00.2 alias iommu_1 on ops amd_iommu_ops end device pci 00.3 alias rcec_1 off end @@ -112,6 +114,7 @@ chip soc/amd/genoa end device domain 2 on + ops genoa_pci_domain_ops device pci 00.0 alias gnb_2 on end device pci 00.2 alias iommu_2 on ops amd_iommu_ops end device pci 00.3 alias rcec_2 off end @@ -152,6 +155,7 @@ chip soc/amd/genoa end device domain 3 on + ops genoa_pci_domain_ops device pci 00.0 alias gnb_3 on end device pci 00.2 alias iommu_3 on ops amd_iommu_ops end device pci 00.3 alias rcec_3 off end |