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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-13 12:34:04 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-09-01 21:07:10 +0000 |
| commit | 6d3682ee9b19b9e6833f38046891132be665c93c (patch) | |
| tree | 5b74f124c101a1b36bd4448956e0358becf61784 /src/soc/amd/genoa/Kconfig | |
| parent | 372c4151d4423788e597c1fdf90e003ce4226649 (diff) | |
soc/amd/genoa: Add minimal viable code for compilation
This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with
amd linker script hooked up.
Default to 64bit code as that will be a sensible default for this
platform (high memory access required for RAS setup).
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I69253466084d17c4359d7e824d69f12490b076e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/genoa/Kconfig')
| -rw-r--r-- | src/soc/amd/genoa/Kconfig | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig new file mode 100644 index 0000000000..f799ac18a2 --- /dev/null +++ b/src/soc/amd/genoa/Kconfig @@ -0,0 +1,73 @@ +config SOC_AMD_GENOA + bool + +if SOC_AMD_GENOA + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select HAVE_EXP_X86_64_SUPPORT + select NO_ECAM_MMCONF_SUPPORT + select NO_MONOTONIC_TIMER + select RESET_VECTOR_IN_RAM + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_NONCAR + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select UNKNOWN_TSC_RATE + +config USE_EXP_X86_64_SUPPORT + default y + +config EARLY_RESERVED_DRAM_BASE + hex + default 0x7000000 + help + This variable defines the base address of the DRAM which is reserved + for usage by coreboot in early stages (i.e. before ramstage is up). + This memory gets reserved in BIOS tables to ensure that the OS does + not use it, thus preventing corruption of OS memory in case of S3 + resume. + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x1000 + +config PSP_APOB_DRAM_ADDRESS + hex + default 0x7001000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PSP_APOB_DRAM_SIZE + hex + default 0x20000 + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Increase this value if preram cbmem console is getting truncated + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x10000 + help + Sets the size of the bootblock stage that should be loaded in DRAM. + This variable controls the DRAM allocation size in linker script + for bootblock stage. + +config ROMSTAGE_ADDR + hex + default 0x7040000 + help + Sets the address in DRAM where romstage should be loaded. + +config ROMSTAGE_SIZE + hex + default 0x80000 + help + Sets the size of DRAM allocation for romstage in linker script. + +endif |