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author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-07 02:32:11 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-08 14:06:10 +0000 |
commit | e4fc7b0ba6e9b1cdf61278ddd7dfbd17af121b56 (patch) | |
tree | 42bfacadc6b37e72d5d4f9b480c9279f0e0d76d0 /src/soc/amd/common | |
parent | e266dacaa103ce399f5bb2d5254f18fc978b934f (diff) |
soc/amd/*/acpi: factor out common get_pstate_info implementation
The implementations of get_pstate_info of Picasso, Cezanne, Mendocino,
Phoenix and Glinda are identical, so factor it out and move it to the
common AMD SoC code. The SoC-specific get_pstate_core_freq and
get_pstate_core_power functions remain in the SoC-specific code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe0494f1747f381a75b3dd71a8cc38fdc6dce042
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/common')
-rw-r--r-- | src/soc/amd/common/block/acpi/cpu_power_state.c | 43 | ||||
-rw-r--r-- | src/soc/amd/common/block/include/amdblocks/cpu.h | 5 |
2 files changed, 46 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/acpi/cpu_power_state.c b/src/soc/amd/common/block/acpi/cpu_power_state.c index cefa0e46a5..dbda621141 100644 --- a/src/soc/amd/common/block/acpi/cpu_power_state.c +++ b/src/soc/amd/common/block/acpi/cpu_power_state.c @@ -7,8 +7,51 @@ #include <console/console.h> #include <cpu/amd/msr.h> #include <cpu/x86/msr.h> +#include <soc/msr.h> #include <types.h> +/* + * Populate structure describing enabled p-states and return count of enabled p-states. + */ +static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, + struct acpi_xpss_sw_pstate *pstate_xpss_values) +{ + msr_t pstate_def; + size_t pstate_count, pstate; + uint32_t pstate_enable, max_pstate; + + pstate_count = 0; + max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; + + for (pstate = 0; pstate <= max_pstate; pstate++) { + pstate_def = rdmsr(PSTATE_MSR(pstate)); + + pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) + >> PSTATE_DEF_HI_ENABLE_SHIFT; + if (!pstate_enable) + continue; + + pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def); + pstate_values[pstate_count].power = get_pstate_core_power(pstate_def); + pstate_values[pstate_count].transition_latency = 0; + pstate_values[pstate_count].bus_master_latency = 0; + pstate_values[pstate_count].control_value = pstate; + pstate_values[pstate_count].status_value = pstate; + + pstate_xpss_values[pstate_count].core_freq = + (uint64_t)pstate_values[pstate_count].core_freq; + pstate_xpss_values[pstate_count].power = + (uint64_t)pstate_values[pstate_count].power; + pstate_xpss_values[pstate_count].transition_latency = 0; + pstate_xpss_values[pstate_count].bus_master_latency = 0; + pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate; + pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate; + pstate_count++; + } + + return pstate_count; +} + static void write_cstate_entry(acpi_cstate_t *entry, const acpi_cstate_t *data, uint32_t cstate_io_base_address) { diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 998ed136fb..76d0326725 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -4,6 +4,7 @@ #define AMD_BLOCK_CPU_H #include <acpi/acpi.h> +#include <cpu/x86/msr.h> #include <types.h> #define MAX_CSTATE_COUNT 8 @@ -14,8 +15,8 @@ unsigned int get_threads_per_core(void); void set_cstate_io_addr(void); void write_resume_eip(void); -size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, - struct acpi_xpss_sw_pstate *pstate_xpss_values); +uint32_t get_pstate_core_freq(msr_t pstate_def); +uint32_t get_pstate_core_power(msr_t pstate_def); const acpi_cstate_t *get_cstate_config_data(size_t *size); #endif /* AMD_BLOCK_CPU_H */ |