diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-05-04 17:34:16 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-06 13:35:30 +0000 |
| commit | 2e4b95da88a5f72269956e34ecaa183cdca48f79 (patch) | |
| tree | 569117889eabbdb0e397ce6267d8e4830cb5fcb2 /src/soc/amd/common | |
| parent | da4e1d780656d6a733f7c2445697466c86a8e901 (diff) | |
soc/amd/common/include/espi: generalize IO/MMIO decode range macros
Sabrina has more eSPI decode ranges than Picasso or Cezanne. Those
registers are however not in one block where it's easy to calculate the
addresses of a register from the index of the decode range. Within one
group of decode range registers it's still easy to calculate the
register address, so move the base address from within the macro to the
instantiation of the macro as a preparation for adding the support for
the additional ranges.
TEST=Timeless build results in identical binary for Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id309d955fa3558d660db37a2075240f938361e83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/espi.h | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index cfba50bd2d..45a220ef7c 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -25,10 +25,10 @@ #define ESPI_MMIO_SIZE_REG0 0x60 #define ESPI_MMIO_SIZE_REG1 0x64 -#define ESPI_IO_RANGE_BASE(range) (ESPI_IO_BASE_REG0 + ((range) & 3) * 2) -#define ESPI_IO_RANGE_SIZE(range) (ESPI_IO_SIZE0 + ((range) & 3)) -#define ESPI_MMIO_RANGE_BASE(range) (ESPI_MMIO_BASE_REG0 + ((range) & 3) * 4) -#define ESPI_MMIO_RANGE_SIZE(range) (ESPI_MMIO_SIZE_REG0 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2) #define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c4d15e4b70..a5f43f4a42 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -72,22 +72,22 @@ static inline uint32_t espi_decode_mmio_range_en_bit(unsigned int idx) static inline unsigned int espi_io_range_base_reg(unsigned int idx) { - return ESPI_IO_RANGE_BASE(idx); + return ESPI_IO_RANGE_BASE_REG(ESPI_IO_BASE_REG0, idx); } static inline unsigned int espi_io_range_size_reg(unsigned int idx) { - return ESPI_IO_RANGE_SIZE(idx); + return ESPI_IO_RANGE_SIZE_REG(ESPI_IO_SIZE0, idx); } static inline unsigned int espi_mmio_range_base_reg(unsigned int idx) { - return ESPI_MMIO_RANGE_BASE(idx); + return ESPI_MMIO_RANGE_BASE_REG(ESPI_MMIO_BASE_REG0, idx); } static inline unsigned int espi_mmio_range_size_reg(unsigned int idx) { - return ESPI_MMIO_RANGE_SIZE(idx); + return ESPI_MMIO_RANGE_SIZE_REG(ESPI_MMIO_SIZE_REG0, idx); } static void espi_enable_decode(uint32_t decode_en) |