soc/amd/common: Add errors for invalid AcpiMmio access

Add a method for the soc/amd/<product> to indicate what AcpiMmio
ranges are supported.  Induce a build error if soc or mainboard
code is added which attempts to use an unsupported block.

This patch attempts to dissuade accessing unsupported blocks without
requiring the complexity of structures or reinitializing at the
beginning of a new stage.

TEST=boot grunt, force build errors by removing blocks in iomap.h
BUG=b:131682806

Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

2 files changed, 115 insertions, 10 deletions

diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index c8c69888c6..edb3882e6f 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -67,6 +67,7 @@ void pm_io_write32(uint8_t reg, uint32_t value)
 
 /* smbus pci read/write - access registers at 0xfed80000 - currently unused */
 
+#if SUPPORTS_ACPIMMIO_SMI_BASE
 /* smi read/write - access registers at 0xfed80200 */
 
 uint8_t smi_read8(uint8_t reg)
@@ -98,7 +99,9 @@ void smi_write32(uint8_t reg, uint32_t value)
 {
 	write32((void *)(ACPIMMIO_SMI_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_SMI_BASE */
 
+#if SUPPORTS_ACPIMMIO_PMIO_BASE
 /* pm read/write - access registers at 0xfed80300 */
 
 u8 pm_read8(u8 reg)
@@ -130,9 +133,13 @@ void pm_write32(u8 reg, u32 value)
 {
 	write32((void *)(ACPIMMIO_PMIO_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_PMIO_BASE */
 
-/* pm2 read/write - access registers at 0xfed80400 - currently unused */
+#if SUPPORTS_ACPIMMIO_PMIO2_BASE
+/* pm2 read/write - access registers at 0xfed80400 - currently unused by any soc */
+#endif
 
+#if SUPPORTS_ACPIMMIO_BIOSRAM_BASE
 /* biosram read/write - access registers at 0xfed80500 */
 
 uint8_t biosram_read8(uint8_t reg)
@@ -169,11 +176,17 @@ void biosram_write32(uint8_t reg, uint32_t value)
 	value >>= 16;
 	biosram_write16(reg + sizeof(uint16_t), value & 0xffff);
 }
+#endif /* SUPPORTS_ACPIMMIO_BIOSRAM_BASE */
 
-/* cmosram read/write - access registers at 0xfed80600 - currently unused */
+#if SUPPORTS_ACPIMMIO_CMOSRAM_BASE
+/* cmosram read/write - access registers at 0xfed80600 - currently unused by any soc */
+#endif
 
-/* cmos read/write - access registers at 0xfed80700 - currently unused */
+#if SUPPORTS_ACPIMMIO_CMOS_BASE
+/* cmos read/write - access registers at 0xfed80700 - currently unused by any soc */
+#endif
 
+#if SUPPORTS_ACPIMMIO_ACPI_BASE
 /* acpi read/write - access registers at 0xfed80800 */
 
 u8 acpi_read8(u8 reg)
@@ -205,7 +218,9 @@ void acpi_write32(u8 reg, u32 value)
 {
 	write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_ACPI_BASE */
 
+#if SUPPORTS_ACPIMMIO_ASF_BASE
 /* asf read/write - access registers at 0xfed80900 */
 
 u8 asf_read8(u8 reg)
@@ -227,7 +242,9 @@ void asf_write16(u8 reg, u16 value)
 {
 	write16((void *)(ACPIMMIO_ASF_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_ASF_BASE */
 
+#if SUPPORTS_ACPIMMIO_SMBUS_BASE
 /* smbus read/write - access registers at 0xfed80a00 */
 
 u8 smbus_read8(u8 reg)
@@ -249,11 +266,17 @@ void smbus_write16(u8 reg, u16 value)
 {
 	write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_SMBUS_BASE */
 
-/* wdt read/write - access registers at 0xfed80b00 - not currently used */
+#if SUPPORTS_ACPIMMIO_WDT_BASE
+/* wdt read/write - access registers at 0xfed80b00 - not currently used by any soc */
+#endif
 
-/* hpet read/write - access registers at 0xfed80c00 - not currently used */
+#if SUPPORTS_ACPIMMIO_HPET_BASE
+/* hpet read/write - access registers at 0xfed80c00 - not currently used by any soc */
+#endif
 
+#if SUPPORTS_ACPIMMIO_IOMUX_BASE
 /* iomux read/write - access registers at 0xfed80d00 */
 
 u8 iomux_read8(u8 reg)
@@ -285,7 +308,9 @@ void iomux_write32(u8 reg, u32 value)
 {
 	write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_IOMUX_BASE */
 
+#if SUPPORTS_ACPIMMIO_MISC_BASE
 /* misc read/write - access registers at 0xfed80e00 */
 
 u8 misc_read8(u8 reg)
@@ -317,13 +342,25 @@ void misc_write32(u8 reg, u32 value)
 {
 	write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_MISC_BASE */
 
-/* dpvga read/write - access registers at 0xfed81400 - not currently used */
+#if SUPPORTS_ACPIMMIO_DPVGA_BASE
+/* dpvga read/write - access registers at 0xfed81400 - not currently used by any soc */
+#endif
 
-/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */
-/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */
-/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */
+#if SUPPORTS_ACPIMMIO_GPIO0_BASE || SUPPORTS_ACPIMMIO_GPIO1_BASE \
+				 || SUPPORTS_ACPIMMIO_GPIO2_BASE
+/*
+ * No helpers are currently in use however common/block//gpio.c accesses
+ * the registers directly.
+ */
+
+/* gpio bk 0 read/write - access registers at 0xfed81500 */
+/* gpio bk 1 read/write - access registers at 0xfed81600 */
+/* gpio bk 2 read/write - access registers at 0xfed81700 */
+#endif
 
+#if SUPPORTS_ACPIMMIO_XHCIPM_BASE
 /* xhci_pm read/write - access registers at 0xfed81c00 */
 
 uint8_t xhci_pm_read8(uint8_t reg)
@@ -355,9 +392,13 @@ void xhci_pm_write32(uint8_t reg, uint32_t value)
 {
 	write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_XHCIPM_BASE */
 
-/* acdc_tmr read/write - access registers at 0xfed81d00 - not currently used */
+#if SUPPORTS_ACPIMMIO_ACDCTMR_BASE
+/* acdc_tmr read/write - access registers at 0xfed81d00 - not currently used by any soc */
+#endif
 
+#if SUPPORTS_ACPIMMIO_AOAC_BASE
 /* aoac read/write - access registers at 0xfed81e00 */
 
 u8 aoac_read8(u8 reg)
@@ -369,3 +410,4 @@ void aoac_write8(u8 reg, u8 value)
 {
 	write8((void *)(ACPIMMIO_AOAC_BASE + reg), value);
 }
+#endif /* SUPPORTS_ACPIMMIO_AOAC_BASE */
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 6be856bc5c..32da867137 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -18,6 +18,69 @@
 #ifndef __AMDBLOCKS_ACPIMMIO_H__
 #define __AMDBLOCKS_ACPIMMIO_H__
 
+/* iomap.h must indicate if the device uses a block, optional if unused. */
+#include <soc/iomap.h>
+#ifndef SUPPORTS_ACPIMMIO_SMI_BASE
+  #define SUPPORTS_ACPIMMIO_SMI_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_PMIO_BASE
+  #define SUPPORTS_ACPIMMIO_PMIO_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_PMIO2_BASE
+  #define SUPPORTS_ACPIMMIO_PMIO2_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_BIOSRAM_BASE
+  #define SUPPORTS_ACPIMMIO_BIOSRAM_BASE	0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_CMOSRAM_BASE
+  #define SUPPORTS_ACPIMMIO_CMOSRAM_BASE	0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_CMOS_BASE
+  #define SUPPORTS_ACPIMMIO_CMOS_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_ACPI_BASE
+  #define SUPPORTS_ACPIMMIO_ACPI_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_ASF_BASE
+  #define SUPPORTS_ACPIMMIO_ASF_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_SMBUS_BASE
+  #define SUPPORTS_ACPIMMIO_SMBUS_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_WDT_BASE
+  #define SUPPORTS_ACPIMMIO_WDT_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_HPET_BASE
+  #define SUPPORTS_ACPIMMIO_HPET_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_IOMUX_BASE
+  #define SUPPORTS_ACPIMMIO_IOMUX_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_MISC_BASE
+  #define SUPPORTS_ACPIMMIO_MISC_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_DPVGA_BASE
+  #define SUPPORTS_ACPIMMIO_DPVGA_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_GPIO0_BASE
+  #define SUPPORTS_ACPIMMIO_GPIO0_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_GPIO1_BASE
+  #define SUPPORTS_ACPIMMIO_GPIO1_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_GPIO2_BASE
+  #define SUPPORTS_ACPIMMIO_GPIO2_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_XHCIPM_BASE
+  #define SUPPORTS_ACPIMMIO_XHCIPM_BASE		0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_ACDCTMR_BASE
+  #define SUPPORTS_ACPIMMIO_ACDCTMR_BASE	0
+#endif
+#ifndef SUPPORTS_ACPIMMIO_AOAC_BASE
+  #define SUPPORTS_ACPIMMIO_AOAC_BASE		0
+#endif
+
 /*
  * The following AcpiMmio register block mapping represents definitions
  * that have been documented in AMD publications.  All blocks aren't