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authorElyes Haouas <ehaouas@noos.fr>2022-07-17 10:22:30 +0200
committerPatrick Georgi <patrick@coreboot.org>2022-07-18 12:44:32 +0000
commit10cd06b1c75e4bc69a1de7e3a70c28ff2e5195fc (patch)
tree955d62a8b6e02c309b5b960fbbcf5644eb1f46e8 /src/soc/amd/common
parentbb5ccbd42fd3e702f71017dd186ae98278ffeeac (diff)
treewide: Don't add bits
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id56310bd616cd19fee5dc934676006b2dc34b1ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65929 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/aoac.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h
index f4a00c73a7..455f32d9e6 100644
--- a/src/soc/amd/common/block/include/amdblocks/aoac.h
+++ b/src/soc/amd/common/block/include/amdblocks/aoac.h
@@ -10,7 +10,7 @@
#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1)
/* Bit definitions for Device D3 Control AOACx0000[40...7E; even byte addresses] */
-#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
+#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) | BIT(1))
#define FCH_AOAC_D0_UNINITIALIZED 0
#define FCH_AOAC_D0_INITIALIZED 1
#define FCH_AOAC_D1_2_3_WARM 2