diff options
| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-09-23 17:16:32 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-24 15:47:59 +0000 |
| commit | c9737c5ce9d5a3c52ae86ea5fe538bec0b305b99 (patch) | |
| tree | b2c0ef3904b50b29add494f5f75b105bb8e2ead5 /src/soc/amd/common/pi/Kconfig | |
| parent | c0982abf86a6312e2572cc0225bbfe702c7ff2bd (diff) | |
soc/amd/common: move block/pi out of the block folder
Since the binaryPI glue code is specific to a binary interface, but not
for a hardware block, move it out of the common blocks directory. This
also brings the binaryPI support in line with the FSP support which is
used on the newer generations. This also drops the
SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already
existing SOC_AMD_PI Kconfig option instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I014e538f2772938031950475e456cc40dd05d74c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/common/pi/Kconfig')
| -rw-r--r-- | src/soc/amd/common/pi/Kconfig | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/amd/common/pi/Kconfig b/src/soc/amd/common/pi/Kconfig new file mode 100644 index 0000000000..7b95364961 --- /dev/null +++ b/src/soc/amd/common/pi/Kconfig @@ -0,0 +1,37 @@ +config SOC_AMD_PI + bool + depends on SOC_AMD_COMMON_BLOCK_ACPI + select CACHE_MRC_SETTINGS + select HAVE_DEBUG_RAM_SETUP + select MRC_WRITE_NV_LATE + help + This option builds functions that interface AMD's AGESA reference + code packaged in the binaryPI form and S3-related functionality. + +if SOC_AMD_PI + +config PI_AGESA_CAR_HEAP_BASE + hex + default 0x400000 + help + The AGESA PI blob may be built to allow an optional callout for + AgesaHeapRebase. If AGESA calls AgesaHeapRebase, this option + determines the location of the heap prior to DRAM availability. + +config PI_AGESA_TEMP_RAM_BASE + hex + default 0x100000 + help + During a boot from S5, AGESA copies its CAR-based heap to a temporary + location in DRAM. Once coreboot has established cbmem, the heap + is moved again. This symbol determines the temporary location for + the heap. + +config PI_AGESA_HEAP_SIZE + hex + default 0x20000 + help + This option determines the amount of space allowed for AGESA heap + prior to DRAM availability. + +endif # SOC_AMD_PI |