diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2022-02-10 17:00:17 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-11 14:07:18 +0000 |
| commit | 08d2016e506153494eb053cd3a2db66f6f780d90 (patch) | |
| tree | b82c7ae6c9a86c9e02214a1c3384840a69d8e313 /src/soc/amd/common/fsp/fsp_validate.c | |
| parent | e527c713bd3533858054fe389ec2a5c93f6d6726 (diff) | |
soc/mediatek/mt8186: Lower SPI NOR speed to 52MHiz
The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's
HW design, which is capable of up to 52MHz. Therefore, lower the speed
to univpll_d3_d8 (52MHz).
BUG=b:218775654
TEST=emerge-corsola coreboot
TEST=Boot time didn't increase significantly
BRAHCH=none
Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/amd/common/fsp/fsp_validate.c')
0 files changed, 0 insertions, 0 deletions