soc/amd: move non-CAR linker scripts to common directory

AMD family 17h and newer don't use cache as RAM, since the RAM is
already initialized by the PSP when the x86 cores are released from
reset. Therefore they use a different linker script as the rest of the
x86 chips in coreboot do. Since there will be support for newer
generations than Picasso will be added, move those linker scripts from
soc/amd/picasso to soc/amd/common/block/cpu/noncar.

TEST=Timeless build of amd/mandolin and amd/gardenia result in identical
binaries.

Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

5 files changed, 222 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index f6756e18f8..826f80bdb5 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -11,3 +11,19 @@ config SOC_AMD_COMMON_BLOCK_CAR
 	  This is only used for AMD CPU before family 17h. From family 17h on
 	  the RAM is already initialized by the PSP before the x86 cores are
 	  released from reset.
+
+config SOC_AMD_COMMON_BLOCK_NONCAR
+	bool
+	default n
+	help
+	  From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
+	  more, since the RAM initialization is already done by the PSP when
+	  the x86 cores are released from reset.
+
+if SOC_AMD_COMMON_BLOCK_NONCAR
+
+config MEMLAYOUT_LD_FILE
+	string
+	default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
+
+endif # SOC_AMD_COMMON_BLOCK_NONCAR
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout.ld b/src/soc/amd/common/block/cpu/noncar/memlayout.ld
new file mode 100644
index 0000000000..6f5d4cf82f
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout.ld
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#if ENV_SEPARATE_VERSTAGE && CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)
+	#include "memlayout_psp_verstage.ld"
+#else
+	#include "memlayout_x86.ld"
+#endif /* ENV_SEPARATE_VERSTAGE && CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) */
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld
new file mode 100644
index 0000000000..aa27bae1d4
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+#include <soc/psp_transfer.h>
+#include <fmap_config.h>
+
+/* TODO: Move defines to SoC-specific header file to allow SoC specific values if needed. */
+
+/*
+ * Start of available space is 0x15000 and this is where the
+ * header for the user app (verstage) must be mapped.
+ * Size is 0x28000 bytes
+ */
+#define PSP_SRAM_START			0x15000
+#define PSP_SRAM_SIZE			160K
+
+#define VERSTAGE_START			0x15000
+
+/*
+ * The temp stack can be made much smaller if needed - even 256 bytes
+ * should be sufficient.  This is just for the function mapping the
+ * actual stack.
+ */
+#define PSP_VERSTAGE_TEMP_STACK_START	0x32000
+#define PSP_VERSTAGE_TEMP_STACK_SIZE	4K
+
+/*
+ * The top of the stack must be 4k aligned, so set the bottom as 4k aligned
+ * and make the size a multiple of 4k
+ */
+#define PSP_VERSTAGE_STACK_START	0x33000
+#define PSP_VERSTAGE_STACK_SIZE		40K
+
+ENTRY(_psp_vs_start)
+SECTIONS
+{
+	SRAM_START(PSP_SRAM_START)
+	_verstage = .;
+
+		.text : { *(PSP_HEADER_DATA) }
+		.text : { *(.text._psp_vs_start) }
+		.text : { *(.text.Main) }
+		.text : { *(.text*) }
+		.rodata : { *(.rodata*) }
+
+		.data : { *(.data*) }
+		.data : { *(PSP_FOOTER_DATA) }
+
+		_bss_start = .;
+		.bss : { *(.bss*) }
+		_bss_end = .;
+
+	ALIGN_COUNTER(64)
+	_everstage = .;
+
+	#include "memlayout_transfer_buffer.inc"
+
+	PSP_VERSTAGE_TEMP_STACK_END = (PSP_VERSTAGE_TEMP_STACK_START + PSP_VERSTAGE_TEMP_STACK_SIZE );
+
+	REGION(stack, PSP_VERSTAGE_STACK_START, PSP_VERSTAGE_STACK_SIZE, 64)
+	PSP_VERSTAGE_STACK_BASE = _stack;
+	PSP_VERSTAGE_STACK_END = _estack;
+	SRAM_END(PSP_SRAM_START + PSP_SRAM_SIZE)
+}
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc
new file mode 100644
index 0000000000..a88e81ac32
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#if CONFIG(VBOOT)
+	ALIGN_COUNTER(64)
+	_transfer_buffer = .;
+	REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4)
+
+	ALIGN_COUNTER(64)
+	VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE)
+#endif
+
+	ALIGN_COUNTER(64)
+	PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
+ 	TIMESTAMP(., TIMESTAMP_BUFFER_SIZE)
+	FMAP_CACHE(., FMAP_SIZE)
+
+#if CONFIG(VBOOT)
+	_etransfer_buffer = .;
+#endif
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
new file mode 100644
index 0000000000..369d43151e
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+#include <soc/psp_transfer.h>
+
+#define EARLY_RESERVED_DRAM_START(addr)		SYMBOL(early_reserved_dram, addr)
+#define EARLY_RESERVED_DRAM_END(addr)		SYMBOL(eearly_reserved_dram, addr)
+
+#define PSP_SHAREDMEM_DRAM_START(addr)		SYMBOL(psp_sharedmem_dram, addr)
+#define PSP_SHAREDMEM_DRAM_END(addr)		SYMBOL(epsp_sharedmem_dram, addr)
+
+/*
+ *
+ *                     +--------------------------------+
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *   reserved_dram_end +--------------------------------+
+ *                     |                                |
+ *                     |       verstage (if reqd)       |
+ *                     |          (VERSTAGE_SIZE)       |
+ *                     +--------------------------------+ VERSTAGE_ADDR
+ *                     |                                |
+ *                     |            FSP-M               |
+ *                     |         (FSP_M_SIZE)           |
+ *                     +--------------------------------+ FSP_M_ADDR
+ *                     |                                |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
+ *                     |           romstage             |
+ *                     |        (ROMSTAGE_SIZE)         |
+ *                     +--------------------------------+ ROMSTAGE_ADDR
+ *                     |           bootblock            |
+ *                     |     (C_ENV_BOOTBLOCK_SIZE)     |
+ *                     +--------------------------------+ BOOTBLOCK_ADDR
+ *                     |          Unused hole           |
+ *                     +--------------------------------+
+ *                     |     FMAP cache (FMAP_SIZE)     |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
+ *                     |  Early Timestamp region (512B) |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
+ *                     |      Preram CBMEM console      |
+ *                     |   (PRERAM_CBMEM_CONSOLE_SIZE)  |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
+ *                     |   PSP shared (vboot workbuf)   |
+ *                     |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE)      |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40
+ *                     |     Transfer Info Structure    |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE
+ *                     |          APOB (64KiB)          |
+ *                     +--------------------------------+ PSP_APOB_DRAM_ADDRESS
+ *                     |        Early BSP stack         |
+ *                     |   (EARLYRAM_BSP_STACK_SIZE)    |
+ * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
+ *                     |              DRAM              |
+ *                     +--------------------------------+ 0x100000
+ *                     |           Option ROM           |
+ *                     +--------------------------------+ 0xc0000
+ *                     |           Legacy VGA           |
+ *                     +--------------------------------+ 0xa0000
+ *                     |              DRAM              |
+ *                     +--------------------------------+ 0x0
+ */
+SECTIONS
+{
+	DRAM_START(0x0)
+
+	EARLY_RESERVED_DRAM_START(CONFIG_EARLY_RESERVED_DRAM_BASE)
+
+	EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE)
+	REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1)
+
+#if CONFIG(VBOOT)
+	PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE)
+#endif
+
+#include "memlayout_transfer_buffer.inc"
+
+#if CONFIG(VBOOT)
+	PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
+#endif
+	_ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
+	_ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
+	BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
+	ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
+	REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1)
+#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
+	VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
+#endif
+
+	EARLY_RESERVED_DRAM_END(.)
+
+	RAMSTAGE(CONFIG_RAMBASE, 8M)
+}
+
+#if ENV_BOOTBLOCK
+
+gdtptr16_offset = gdtptr16 & 0xffff;
+nullidt_offset = nullidt & 0xffff;
+
+SECTIONS {
+	/* Trigger an error if I have an unusable start address */
+	_TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
+	_bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
+
+	. = CONFIG_X86_RESET_VECTOR;
+	.reset . : {
+		*(.reset);
+		. = 15;
+		BYTE(0x00);
+	}
+}
+#endif  /* ENV_BOOTBLOCK */