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authorFelix Held <felix-coreboot@felixheld.de>2022-02-17 17:22:25 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-18 17:14:12 +0000
commit63226901c758e6a8374329587f5393d9af401d13 (patch)
tree3e940ad86935b6f6734e6f5e2f4486bb91e3ad3d /src/soc/amd/common/block
parent14976dbed01c08ca875f0d32053012b4a512b626 (diff)
soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAP
Also add the Makefile dependency on the fmap_config.h file to make sure that this file already exists when it's included. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block')
-rw-r--r--src/soc/amd/common/block/apob/Makefile.inc4
-rw-r--r--src/soc/amd/common/block/apob/apob_cache.c6
2 files changed, 7 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc
index 6e217df648..56cd5e12de 100644
--- a/src/soc/amd/common/block/apob/Makefile.inc
+++ b/src/soc/amd/common/block/apob/Makefile.inc
@@ -1,4 +1,8 @@
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y)
romstage-y += apob_cache.c
ramstage-y += apob_cache.c
+
+$(call src-to-obj,romstage,$(dir)/apob_cache.c) : $(obj)/fmap_config.h
+$(call src-to-obj,ramstage,$(dir)/apob_cache.c) : $(obj)/fmap_config.h
+
endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB
diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c
index bdacd81ba4..b932458ec2 100644
--- a/src/soc/amd/common/block/apob/apob_cache.c
+++ b/src/soc/amd/common/block/apob/apob_cache.c
@@ -9,15 +9,15 @@
#include <commonlib/region.h>
#include <console/console.h>
#include <fmap.h>
+#include <fmap_config.h>
#include <spi_flash.h>
#include <stdint.h>
#include <string.h>
#include <thread.h>
#include <timestamp.h>
-#define DEFAULT_MRC_CACHE "RW_MRC_CACHE"
-/* PSP requires this value to be 64KiB */
-#define DEFAULT_MRC_CACHE_SIZE 0x10000
+#define DEFAULT_MRC_CACHE "RW_MRC_CACHE"
+#define DEFAULT_MRC_CACHE_SIZE FMAP_SECTION_RW_MRC_CACHE_SIZE
#if !CONFIG_PSP_APOB_DRAM_ADDRESS
#error Incorrect APOB configuration setting(s)