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authorRaul E Rangel <rrangel@chromium.org>2021-02-09 10:56:47 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-02-10 19:00:22 +0000
commit4f1147b54124609284e390b9a1176a90877848f5 (patch)
tree6bd4b97e9963db8c605e5740f7eba056ab2c5ffe /src/soc/amd/common/block
parentf87427f1a4303d6cab26f29641831b4d3dec8451 (diff)
soc/amd/picasso: Add SPI registers
The picasso SPI registers are different than the ones defined in amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the PSP_SPI_MMIO_SEL bit has been added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block')
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