soc/amd/common: factor out SMN access function from SMU code

The SMU mailbox interface gets accessed over the SMN register space, so
factor out those access functions into a separate common code SMN access
building block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

3 files changed, 34 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/smn/Kconfig b/src/soc/amd/common/block/smn/Kconfig
new file mode 100644
index 0000000000..a076bba63e
--- /dev/null
+++ b/src/soc/amd/common/block/smn/Kconfig
@@ -0,0 +1,4 @@
+config SOC_AMD_COMMON_BLOCK_SMN
+	bool
+	help
+	  Select this option to add functions to access the SMN register space to the build.
diff --git a/src/soc/amd/common/block/smn/Makefile.inc b/src/soc/amd/common/block/smn/Makefile.inc
new file mode 100644
index 0000000000..01de303606
--- /dev/null
+++ b/src/soc/amd/common/block/smn/Makefile.inc
@@ -0,0 +1,8 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMN),y)
+
+bootblock-y += smn.c
+romstage-y += smn.c
+ramstage-y += smn.c
+smm-y += smn.c
+
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMN
diff --git a/src/soc/amd/common/block/smn/smn.c b/src/soc/amd/common/block/smn/smn.c
new file mode 100644
index 0000000000..055f732cf7
--- /dev/null
+++ b/src/soc/amd/common/block/smn/smn.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/smn.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <types.h>
+
+/* SMN registers accessed indirectly using an index/data pair in D0F00 config space */
+#define SMN_INDEX_ADDR		0xb8 /* 32 bit */
+#define SMN_DATA_ADDR		0xbc /* 32 bit */
+
+uint32_t smn_read32(uint32_t reg)
+{
+	pci_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
+	return pci_read_config32(SOC_GNB_DEV, SMN_DATA_ADDR);
+}
+
+void smn_write32(uint32_t reg, uint32_t val)
+{
+	pci_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
+	pci_write_config32(SOC_GNB_DEV, SMN_DATA_ADDR, val);
+}