soc/amd/common: Update SPI based on Kconfig & EFS instead of devtree

Get the settings for fast-read and mode from EFS, and reprogram those.
Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings.

BUG=b:195943311
TEST=Boot and see that SPI was set to the correct speed & mode

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

2 files changed, 27 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc
index 3bb03f7e81..db9ebda594 100644
--- a/src/soc/amd/common/block/psp/Makefile.inc
+++ b/src/soc/amd/common/block/psp/Makefile.inc
@@ -22,4 +22,6 @@ ramstage-y += psp_gen2.c
 smm-y += psp_gen2.c
 smm-y += psp_smm_gen2.c
 
+bootblock-y += psp_efs.c
+
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2
diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c
new file mode 100644
index 0000000000..b0397f6ae8
--- /dev/null
+++ b/src/soc/amd/common/block/psp/psp_efs.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/psp_efs.h>
+#include <arch/mmio.h>
+#include <types.h>
+
+struct _embedded_firmware *efs = (struct _embedded_firmware *)EFS_ADDRESS;
+
+bool efs_is_valid(void)
+{
+	if (efs->signature != EMBEDDED_FW_SIGNATURE)
+		return false;
+
+	return true;
+}
+
+bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed)
+{
+	if (!efs_is_valid())
+		return false;
+
+	*mode = efs->SPI_MODE_FIELD;
+	*speed = efs->SPI_SPEED_FIELD;
+	return true;
+}