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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-10-27 20:12:46 -0600
committerAaron Durbin <adurbin@chromium.org>2017-11-06 22:21:50 +0000
commit3727708aefb03ac7ca0f15246cfded18b85b49b3 (patch)
treef4bbde857fa825b3252408f095237c7c962fa8ba /src/soc/amd/common/block/psp
parent1ab8c01050c539b1af9edc5d2fd13a79bb71d053 (diff)
soc/amd/common/psp: Require PSP PCI definition in SOC
Remove the definition for the PSP PCI device from the common PSP code. Any APU using this source should have its own definitions, and this allows for the device to move within the config space. Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block/psp')
-rw-r--r--src/soc/amd/common/block/psp/psp.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index 788de2ceea..8b3605e6fa 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -127,8 +127,8 @@ static int send_psp_command(u32 command, void *buffer)
if (!mbox)
return -PSPSTS_NOBASE;
- command_reg = pci_read_config32(PSP_DEV, PCI_COMMAND);
- pci_write_config32(PSP_DEV, PCI_COMMAND, command_reg |
+ command_reg = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
+ pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, command_reg |
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* check for PSP error conditions */
@@ -168,7 +168,7 @@ static int send_psp_command(u32 command, void *buffer)
}
exit:
/* restore command register to original value */
- pci_write_config32(PSP_DEV, PCI_COMMAND, command_reg);
+ pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, command_reg);
return status;
}