include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition

The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it
there. The soc/amd/* code itself uses the bit definition when accessing
HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition.

Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR,
since that bit isn't in that MSR.

TEST=Checked the code and the corresponding BKDG/PPR.

Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c
index b103b3e629..f919668190 100644
--- a/src/soc/amd/common/block/psp/psp_smm.c
+++ b/src/soc/amd/common/block/psp/psp_smm.c
@@ -53,7 +53,7 @@ int psp_notify_smm(void)
 	msr = rdmsr(SMM_ADDR_MSR);
 	buffer.req.smm_base = ((uint64_t)msr.hi << 32) | msr.lo;
 	msr = rdmsr(SMM_MASK_MSR);
-	msr.lo &= 0xffff0000; /* mask SMM_LOCK and SMM_TSEG_VALID and reserved bits */
+	msr.lo &= 0xffff0000; /* mask SMM_TSEG_VALID and reserved bits */
 	buffer.req.smm_mask = ((uint64_t)msr.hi << 32) | msr.lo;
 
 	soc_fill_smm_trig_info(&buffer.req.smm_trig_info);