From 357cc6552ab6f0202c329e9565b278366e2494b8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 9 Jul 2020 00:04:22 +0200 Subject: include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it there. The soc/amd/* code itself uses the bit definition when accessing HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition. Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR, since that bit isn't in that MSR. TEST=Checked the code and the corresponding BKDG/PPR. Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309 Reviewed-by: Raul Rangel Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/psp/psp_smm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/amd/common/block/psp/psp_smm.c') diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index b103b3e629..f919668190 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -53,7 +53,7 @@ int psp_notify_smm(void) msr = rdmsr(SMM_ADDR_MSR); buffer.req.smm_base = ((uint64_t)msr.hi << 32) | msr.lo; msr = rdmsr(SMM_MASK_MSR); - msr.lo &= 0xffff0000; /* mask SMM_LOCK and SMM_TSEG_VALID and reserved bits */ + msr.lo &= 0xffff0000; /* mask SMM_TSEG_VALID and reserved bits */ buffer.req.smm_mask = ((uint64_t)msr.hi << 32) | msr.lo; soc_fill_smm_trig_info(&buffer.req.smm_trig_info); -- cgit v1.2.3