diff options
| author | Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> | 2020-03-05 11:44:24 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-04-13 12:39:12 +0000 |
| commit | d6b7236732d8cc74545849f4b81af1d33e8758e2 (patch) | |
| tree | 8203c3ad9d18a49d4bc243e0bdbe02b0fad77be0 /src/soc/amd/common/block/psp/Kconfig | |
| parent | a67c753d554c730c794726b1b65d07c9c383e264 (diff) | |
soc/amd/common/psp: Split mailbox support into v1 and v2
Family 17h redefines the PSP command and status, and therefore the
steps required to send commands via the mailbox. Convert the existing
version into a v1 and add a v2. New Kconfig options allow the soc to
choose v1 vs. v2.
The v2 PSP begins responding to the mailbox command when the full
bit range is written. Define the new mailbox as a union of a u32
and a structure.
Additional PSP details may be found in the NDA publication (#55758)
AMD Platform Security Processor BIOS Architecture Design Guide for
AMD Family 17h Processors
Change the existing two soc functions that return pointers to void
pointers.
BUG=b:153677737
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4d358fdae07da471640856f57568059e9487f6a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block/psp/Kconfig')
| -rw-r--r-- | src/soc/amd/common/block/psp/Kconfig | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 0517a2f33f..9466cc6abd 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -3,7 +3,18 @@ config SOC_AMD_COMMON_BLOCK_PSP default n help This option builds in the Platform Security Processor initialization - functions. + functions. Do not select this directly in SoC code, select + SOC_AMD_COMMON_BLOCK_PSP_GENx instead. + +config SOC_AMD_COMMON_BLOCK_PSP_GEN1 + bool + default n + select SOC_AMD_COMMON_BLOCK_PSP + +config SOC_AMD_COMMON_BLOCK_PSP_GEN2 + bool + default n + select SOC_AMD_COMMON_BLOCK_PSP config SOC_AMD_PSP_SELECTABLE_SMU_FW bool |