diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-09 11:24:13 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-10 19:00:49 +0000 |
| commit | 466edb51b4b0c19486f14f43bee8d6834c52abc9 (patch) | |
| tree | 9ebb3277717e3e0728bb645b06e5f5ade3965394 /src/soc/amd/common/block/lpc | |
| parent | 6ba1fcac3402a8719b6d080eb78e67b059a9b2ad (diff) | |
soc/amd/common/blocks/lpc: Remove common SPI registers
Use the SoC versions instead.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block/lpc')
| -rw-r--r-- | src/soc/amd/common/block/lpc/lpc.c | 3 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/lpc_util.c | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 7f3bea0da7..d68814ba9f 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -16,8 +16,9 @@ #include <amdblocks/espi.h> #include <amdblocks/lpc.h> #include <soc/acpi.h> -#include <soc/southbridge.h> #include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/southbridge.h> /* Most systems should have already enabled the bridge */ void __weak soc_late_lpc_bridge_enable(void) { } diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index eb129dc00d..fb231dd7e9 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -8,6 +8,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> #include <soc/iomap.h> +#include <soc/lpc.h> #include <soc/southbridge.h> /* The LPC-ISA bridge is always at D14F3 */ |