diff options
author | Martin Roth <martinroth@chromium.org> | 2020-07-06 23:35:40 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:04:25 +0000 |
commit | f09b4b6beed16d964527d26700df6d350e3aeab0 (patch) | |
tree | a4bd668cc39bbcac6dd41e67bc9e12ce07c635c4 /src/soc/amd/common/block/include | |
parent | 5a1e2d3f631a855c869efb1a43e721f7251904ea (diff) |
soc/amd/common: Refactor and consolidate code for spi base
Previously, the spi base address code was using a number of different
functions in a way that didn't work for use on the PSP.
This patch consolidates all of that to a single saved value that gets
the LPC SPI base address by default on X86, and allows the PSP to set
it to a different value.
BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/include')
-rw-r--r-- | src/soc/amd/common/block/include/amdblocks/spi.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index d226e0c05d..fa52da7535 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -3,6 +3,8 @@ #ifndef __AMDBLOCKS_SPI_H__ #define __AMDBLOCKS_SPI_H__ +#include <stdint.h> + #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) @@ -94,4 +96,10 @@ void fch_spi_early_init(void); */ void fch_spi_config_modes(void); +/* Set the SPI base address variable */ +void spi_set_base(void *base); + +/* Get the SPI base address variable's value */ +uintptr_t spi_get_bar(void); + #endif /* __AMDBLOCKS_SPI_H__ */ |