diff options
| author | Martin Roth <martinroth@chromium.org> | 2021-08-11 13:21:20 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-30 18:53:56 +0000 |
| commit | e582e710b8ed6315a2a62b8c6d745af218d434cb (patch) | |
| tree | 90ac010b692e563eaa8edc14892b626241740969 /src/soc/amd/common/block/include | |
| parent | 0032bfa5c5f93d3530fee90a021829db79b328f1 (diff) | |
soc/amd/common: Show current SPI speeds and modes
This patch adds code to print the current SPI speeds for each of the 4
different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays
the SPI mode and whether or not SPI100 mode is enabled.
BUG=b:194919326
TEST: Display the speed, change speeds, show that new speeds are the
expected values.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/common/block/include')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/spi.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index a551151d46..c4ad44f8a4 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -32,6 +32,12 @@ enum spi_read_mode { #define SPI100_ENABLE 0x20 #define SPI_USE_SPI100 BIT(0) +#define DECODE_SPI_MODE_BITS(x) ((x) & SPI_READ_MODE_MASK) +#define DECODE_SPI_MODE_UPPER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 28) & 0x06) +#define DECODE_SPI_MODE_LOWER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 18) & 0x01) +#define DECODE_SPI_READ_MODE(x) (DECODE_SPI_MODE_UPPER_BITS(x) | \ + DECODE_SPI_MODE_LOWER_BITS(x)) + /* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ #define SPI100_SPEED_CONFIG 0x22 enum spi100_speed { @@ -53,6 +59,13 @@ enum spi100_speed { #define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) +#define DECODE_SPEED_MASK 0x07 +#define DECODE_SPEED_MODE(x, shift) (((x) >> shift) & DECODE_SPEED_MASK) +#define DECODE_SPI_NORMAL_SPEED(x) DECODE_SPEED_MODE(x, 12) +#define DECODE_SPI_FAST_SPEED(x) DECODE_SPEED_MODE(x, 8) +#define DECODE_SPI_ALT_SPEED(x) DECODE_SPEED_MODE(x, 4) +#define DECODE_SPI_TPM_SPEED(x) DECODE_SPEED_MODE(x, 0) + #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) @@ -91,6 +104,9 @@ void fch_spi_early_init(void); /* Set the SPI base address variable */ void spi_set_base(void *base); +/* Show the SPI settings */ +void show_spi_speeds_and_modes(void); + /* Get the SPI base address variable's value */ uintptr_t spi_get_bar(void); uint8_t spi_read8(uint8_t reg); |