soc/amd/cezanne: Factor out common GPP clk req code

Factor out the `gpp_dxio_update_clk_req_config` function as it will be
useful for other AMD SoCs.

BUG=b:250009974
TEST=Ran on nipperkin device, verified clk req settings match enabled
devices

Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 17 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
new file mode 100644
index 0000000000..32dadf45b2
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_PCI_GPP_H
+#define AMD_BLOCK_PCI_GPP_H
+
+#include <soc/platform_descriptors.h>
+
+enum gpp_clk_req {
+	GPP_CLK_ON,  /* GPP clock always on; default */
+	GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
+	GPP_CLK_OFF, /* GPP clk off */
+};
+
+void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config,
+					 size_t gpp_clk_config_num);
+
+#endif