soc/amd/cezanne,picasso: factor out common early non-car cache setup

This implementation is the same for all SoC that select
SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR
CPU support code folder.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
index 0627bc1377..6576c3b993 100644
--- a/src/soc/amd/common/block/include/amdblocks/cpu.h
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -3,6 +3,7 @@
 #ifndef AMD_BLOCK_CPU_H
 #define AMD_BLOCK_CPU_H
 
+void early_cache_setup(void);
 int get_cpu_count(void);
 void set_cstate_io_addr(void);
 void write_resume_eip(void);