diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-02-10 11:00:46 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 16:17:24 +0000 |
| commit | 0fcf8356eb5430a202095608b8c9f874086ee87a (patch) | |
| tree | 4149cae552a04a7656ef63888893860dcaafef56 /src/soc/amd/common/block/include | |
| parent | df81e07c37fe50ef225ddf2fa5c94c2e2ada013f (diff) | |
soc/amd/common/acp: add acp_gen2
The gen2 ACP register definitions and locations are different from
previous models. Specific code is refactored into acp_gen1 and acp_gen2.
Update ACP register locations and definitions for gen2.
Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common/block/include')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/acp.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/acp.h b/src/soc/amd/common/block/include/amdblocks/acp.h index 13254e4c0a..04112ca272 100644 --- a/src/soc/amd/common/block/include/amdblocks/acp.h +++ b/src/soc/amd/common/block/include/amdblocks/acp.h @@ -7,12 +7,29 @@ struct acp_config { enum { +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN2) + ACP_PINS_HDA_3SDI = 1, /* HDA 3xSDI */ + ACP_PINS_HDA_1SDI_1SW = 2, /* HDA 1xSDI, SW w/Data0 */ + ACP_PINS_4SW_1SW = 3, /* SW w/Data0-3, SW w/Data0 */ + ACP_PINS_HDA_3SDI_PDM2 = 4, /* HDA 3xSDI, PDM 2CH */ + ACP_PINS_HDA_1SDI_PDM6 = 5, /* HDA 1xSDI, PDM 6CH */ + ACP_PINS_HDA_1SDI_1SW_PDM2 = 6, /* HDA 1xSDI, SW w/Data0, PDM 2CH */ + ACP_PINS_4SW_PDM6 = 7, /* SW w/Data0-3, PDM 6CH */ + ACP_PINS_4SW_1SW_PDM2 = 8, /* SW w/Data0-3, SW w/Data0, PDM 2CH */ + ACP_PINS_I2S = 9, /* 3xI2S, Refclk, Intr */ + ACP_PINS_HDA_3SDI_PDM6_I2S = 10,/* HDA 3xSDI, PDM 6CH, I2S */ + ACP_PINS_HDA_3SDI_PDM8 = 11, /* HDA 3xSDI, PDM 8CH */ + ACP_PINS_HDA_1SDI_1SW_PDM6_I2S = 12,/* HDA 1xSDI, SW w/Data0, PDM 6CH, I2S */ + ACP_PINS_4SW_1SW_PDM6_I2S = 13, /* SW w/Data0-3, SW w/Data0, PDM 6CH, I2S */ + ACP_PINS_4SW_1SW_PDM8 = 14, /* SW w/Data0-3, SW w/Data0, PDM 8CH */ +#else I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ I2S_PINS_I2S_TDM = 4, I2S_PINS_UNCONF = 7, /* All pads will be input mode */ +#endif } acp_pin_cfg; /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ |