diff options
| author | Martin Roth <martinroth@chromium.org> | 2021-08-09 13:47:48 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-30 18:34:48 +0000 |
| commit | b5b1c5a7da72a21e09f6476172c5ff0068b13f7d (patch) | |
| tree | e135ce878b328951018909a389597e6876d6bd82 /src/soc/amd/common/block/include/amdblocks | |
| parent | f363ad4acf7b749deb2c546890101d19bfb6d75d (diff) | |
soc/amd/common: Update SPI based on Kconfig & EFS instead of devtree
Get the settings for fast-read and mode from EFS, and reprogram those.
Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings.
BUG=b:195943311
TEST=Boot and see that SPI was set to the correct speed & mode
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/psp_efs.h | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h new file mode 100644 index 0000000000..7afd295df3 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#ifndef AMD_COMMON_PSP_EFS_H +#define AMD_COMMON_PSP_EFS_H + +#include <types.h> + +#define EFS_OFFSET (0xffffff - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000 + 1) +#define EFS_ADDRESS (0xff000000 + EFS_OFFSET) + +#define EMBEDDED_FW_SIGNATURE 0x55aa55aa + +#if CONFIG(SOC_AMD_STONEYRIDGE) + #define SPI_MODE_FIELD spi_readmode_f15_mod_60_6f + #define SPI_SPEED_FIELD fast_speed_new_f15_mod_60_6f +#elif CONFIG(SOC_AMD_PICASSO) + #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f + #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_00_2f +#elif CONFIG(SOC_AMD_CEZANNE) + #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f + #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f +#else + #error <Error: Unknown Processor> +#endif + + +struct second_gen_efs { /* todo: expand for Server products */ + int gen:1; /* Client products only use bit 0 */ + int reserved:31; +} __attribute__((packed)); + +/* Copied from coreboot/util/amdfwtool.h */ +typedef struct _embedded_firmware { + uint32_t signature; /* 0x55aa55aa */ + uint32_t imc_entry; + uint32_t gec_entry; + uint32_t xhci_entry; + uint32_t psp_entry; + uint32_t comboable; + uint32_t bios0_entry; + uint32_t bios1_entry; + uint32_t bios2_entry; + struct second_gen_efs efs_gen; + uint32_t bios3_entry; + uint32_t reserved_2Ch; + uint32_t promontory_fw_ptr; + uint32_t lp_promontory_fw_ptr; + uint32_t reserved_38h; + uint32_t reserved_3Ch; + uint8_t spi_readmode_f15_mod_60_6f; + uint8_t fast_speed_new_f15_mod_60_6f; + uint8_t reserved_42h; + uint8_t spi_readmode_f17_mod_00_2f; + uint8_t spi_fastspeed_f17_mod_00_2f; + uint8_t qpr_dummy_cycle_f17_mod_00_2f; + uint8_t reserved_46h; + uint8_t spi_readmode_f17_mod_30_3f; + uint8_t spi_fastspeed_f17_mod_30_3f; + uint8_t micron_detect_f17_mod_30_3f; + uint8_t reserved_4Ah; + uint8_t reserved_4Bh; + uint32_t reserved_4Ch; +} __attribute__((packed, aligned(16))) embedded_firmware; + +bool efs_is_valid(void); +bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed); + +#endif /* AMD_COMMON_PSP_EFS_H */ |