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authorFelix Held <felix-coreboot@felixheld.de>2023-05-05 15:20:15 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-06-07 00:22:09 +0000
commit8cab80c84f2be22e1f45a2b31c8019695b70abb2 (patch)
tree39d4f4652869298f2a1ab41149ba9a73e1364b96 /src/soc/amd/common/block/include/amdblocks
parentb56ea2503f77f8c9962c55e65447030e657408f7 (diff)
soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge
Now that Stoneyridge is the only AMD SoC that still needs the part of the SSDT that contains the TOM1 and TOM2, move it from the common code to the Stoneyridge northbridge code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9091360d6a82183092ef75417ad652523babe075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75564 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpi.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h
index 91051841f5..682f8ca7fd 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpi.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpi.h
@@ -54,8 +54,6 @@ struct chipset_power_state {
unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current,
struct acpi_rsdp *rsdp);
-void acpi_fill_root_complex_tom(const struct device *device);
-
uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp,
uintptr_t current);