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authorRaul E Rangel <rrangel@chromium.org>2021-05-07 14:25:09 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-05-09 18:09:05 +0000
commit7502e10fdfe4085c5f7d03b0b29d0f7fb9b390fe (patch)
tree1ad2caa0d9719b6c7f54603bc0a1ad378540ff32 /src/soc/amd/common/block/include/amdblocks
parent1d1dbc4cfabf569b7d352dbcb5cee686fd5882d5 (diff)
soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT
This is loosely based off of picasso/pcie_gpp.c. This version uses the acpigen_write_PRT_X methods to write the actual records. There are also two functions, 1 for using the GNB, and one for using the FCH. The FCH one is useful when the GNB IO-APIC has not been initialized. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/amd_pci_util.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
index 83922c9468..0a4061f631 100644
--- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
+++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
@@ -5,6 +5,7 @@
#include <types.h>
#include <soc/amd_pci_int_defs.h>
+#include <device/device.h>
/* FCH index/data registers */
#define PCI_INTR_INDEX 0xc00
@@ -60,4 +61,7 @@ const struct pci_routing_info *get_pci_routing_info(unsigned int devfn);
unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin);
+void acpigen_write_pci_GNB_PRT(const struct device *dev);
+void acpigen_write_pci_FCH_PRT(const struct device *dev);
+
#endif /* AMD_BLOCK_PCI_UTIL_H */