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authorRaul E Rangel <rrangel@chromium.org>2020-05-01 14:04:08 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-05-05 12:59:33 +0000
commit314c716aff9895221f1f5b8bef4d3889a7749c0a (patch)
treea1520b205e0f624a9e235433d3d7f7129369ca52 /src/soc/amd/common/block/include/amdblocks
parent65cc80f740a736d3b947268c157d3331a7cec922 (diff)
soc/amd/common/block/lpc: Add lpc_disable_spi_rom_sharing
If a Picasso platform wants to use GPIO 67 it must disable ROM sharing. Otherwise ROM access is incredibly slow. BUG=b:153502861 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9ab3803a2f56f68c1164bd241fc3917a3ffcf2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/lpc.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index dc33073d3e..1d74823542 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -10,6 +10,8 @@
/* PCI registers for D14F3 */
#define LPC_PCI_CONTROL 0x40
#define LEGACY_DMA_EN BIT(2)
+#define VW_ROM_SHARING_EN BIT(3)
+#define EXT_ROM_SHARING_EN BIT(4)
#define LPC_IO_PORT_DECODE_ENABLE 0x44
#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)
@@ -148,6 +150,7 @@ void lpc_tpm_decode(void);
void lpc_tpm_decode_spi(void);
void lpc_enable_rom(void);
void lpc_enable_spi_prefetch(void);
+void lpc_disable_spi_rom_sharing(void);
/**
* @brief Find the size of a particular wide IO