diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2019-08-21 09:19:13 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-09-21 20:34:27 +0000 |
| commit | e512bce18967d52675653351b7154dc1ab75341d (patch) | |
| tree | 3fab28213ff19244241296d933d1a1a33261a2fa /src/soc/amd/common/block/include/amdblocks/lpc.h | |
| parent | 524bcbb494d5486470b993d7d717234d5781da03 (diff) | |
soc/amd/common/block: Create new SPI code
Create a new SPI code that overrides flash operations and uses the SPI
controller within the FCH to its fullest.
Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public)
BUG=b:136595978
TEST=Build and boot grunt using this code, with debug enabled. Check
output.
Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks/lpc.h')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/lpc.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index f956ba3aa9..11880eb3e6 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -90,6 +90,14 @@ #define DECODE_IO_PORT_ENABLE0_H BIT(0) #define LPC_MEM_PORT1 0x4c +#define ROM_PROTECT_RANGE0 0x50 +#define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ +#define ROM_RANGE_WP BIT(10) +#define ROM_RANGE_RP BIT(9) +#define RANGE_UNIT BIT(8) +#define RANGE_ADDR_MASK 0x000000ff /* Range defined by bits 7-0 */ +#define ROM_PROTECT_RANGE_REG(n) (ROM_PROTECT_RANGE0 + (4 * n)) +#define MAX_ROM_PROTECT_RANGES 4 #define LPC_MEM_PORT0 0x60 /* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. |