From e512bce18967d52675653351b7154dc1ab75341d Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Wed, 21 Aug 2019 09:19:13 -0700 Subject: soc/amd/common/block: Create new SPI code Create a new SPI code that overrides flash operations and uses the SPI controller within the FCH to its fullest. Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public) BUG=b:136595978 TEST=Build and boot grunt using this code, with debug enabled. Check output. Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/soc/amd/common/block/include/amdblocks/lpc.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/amd/common/block/include/amdblocks/lpc.h') diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index f956ba3aa9..11880eb3e6 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -90,6 +90,14 @@ #define DECODE_IO_PORT_ENABLE0_H BIT(0) #define LPC_MEM_PORT1 0x4c +#define ROM_PROTECT_RANGE0 0x50 +#define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ +#define ROM_RANGE_WP BIT(10) +#define ROM_RANGE_RP BIT(9) +#define RANGE_UNIT BIT(8) +#define RANGE_ADDR_MASK 0x000000ff /* Range defined by bits 7-0 */ +#define ROM_PROTECT_RANGE_REG(n) (ROM_PROTECT_RANGE0 + (4 * n)) +#define MAX_ROM_PROTECT_RANGES 4 #define LPC_MEM_PORT0 0x60 /* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. -- cgit v1.2.3