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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-22 23:11:11 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-25 01:14:40 +0000 |
| commit | f070253659d0e0aaeefa2a65b42cc1fa448e5829 (patch) | |
| tree | 51087477bd728e1c88e8d312e4e3f1ca7a65c3f7 /src/soc/amd/common/block/cpu | |
| parent | 5a2feeda39dfc5090c3a3d3bf5e4d8c0af3c650d (diff) | |
soc/amd/common/block/cpu/mca/mcax: add comment about McaXEnable bit
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN
APU that the McaXEnable bit is set in the CONFIG registers of all used
MCAX banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block/cpu')
| -rw-r--r-- | src/soc/amd/common/block/cpu/mca/mcax.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c index a4b5c59b03..46c72f00a8 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax.c +++ b/src/soc/amd/common/block/cpu/mca/mcax.c @@ -7,6 +7,9 @@ #include <types.h> #include "mca_common_defs.h" +/* The McaXEnable bit in the config registers of the available MCAX banks is already set by the + FSP, so no need to set it here again. */ + bool mca_skip_check(void) { /* On Zen-based CPUs/APUs the MCA(X) status register have a defined state even in the |