diff options
| author | Richard Spiegel <richard.spiegel@silverbackltd.com> | 2018-03-05 08:11:50 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-16 19:01:46 +0000 |
| commit | a9f49366c09f8902a13221185449a1d0870af1c6 (patch) | |
| tree | 701c79a43de4c8d48cc3102bb12b980b582731e4 /src/soc/amd/common/block/cpu | |
| parent | 013f1024c3f96ff9a59b70ae6a83ea3d7e9071dc (diff) | |
soc/amd/stoneyridge: Create a HALT_THIS_AP callout
It was required for all cores use the same CAR teardown function
(exit_car.S and gcccar.inc). AGESA has already been modified to do the
AP to do the call out. Create assembly code to call chipset_teardown_car
and then enter an endless loop with halt instruction. Then create the
call out that will call this new assembly code.
BUG=b:70338633
AGESA COMMIT=3313d277
TEST=Created a debug version of AGESA that would print the returned
status of HALT_THIS_AP. Build code without the fix, see the return.
Build code with the fix, see that there's no return.
Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/24999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/common/block/cpu')
| -rw-r--r-- | src/soc/amd/common/block/cpu/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/car/ap_exit_car.S | 61 |
2 files changed, 65 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index ecc9afbc6f..fed208a378 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1,3 +1,7 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/ap_exit_car.S +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S + postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S + romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S diff --git a/src/soc/amd/common/block/cpu/car/ap_exit_car.S b/src/soc/amd/common/block/cpu/car/ap_exit_car.S new file mode 100644 index 0000000000..5d3e13b1a2 --- /dev/null +++ b/src/soc/amd/common/block/cpu/car/ap_exit_car.S @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +.code32 + +#include <cpu/x86/cr.h> + +.globl ap_teardown_car +ap_teardown_car: + pop %esi /* return address, don't care */ + pop %esi /* flags */ + + /* chipset_teardown_car() is expected to disable cache-as-ram. */ + call chipset_teardown_car + + /* + * Check flags requirements (0 = FALSE, 1 = TRUE) : + * bit 0 = ExecWbinvd + * bit 1 = CacheEn + */ + + /* + * TODO: Either use or remove this code - we'll node if the code + * is needed when 3 conditions happens: + * 1) This code is in place + * 2) AGESA code that calls HALT_THIS_AP is in place + * 3) We boot to OS, go to S3 and resume. + * If S3 resume fails, this code might be needed, if S3 resume + * is successful then the code can be removed. + */ + + /* + * Commented out until defined if needed or not. + * test %esi, 1 + * jz 1f + * wbinvd + * 1: + */ + + test %esi, 2 + jz 2f + /* Enable cache */ + mov %cr0, %eax + and $(~(CR0_CD | CR0_NW)), %eax + mov %eax, %cr0 +2: + cli + hlt + jmp 2b |