diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2022-01-18 15:29:54 -0700 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-01-23 16:42:48 +0000 |
| commit | 86302a806c5cc9b575424305e761753710417692 (patch) | |
| tree | 6d3c1305d29ad1a9369770e7a9a2ac03b03c4f4b /src/soc/amd/common/block/cpu | |
| parent | 1e1aa0ca4d4d5ae9d0b4917220cc72f9c441b8a2 (diff) | |
soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE
This change splits the size of the console transfer region and size of
the bootblock/romstage Pre-RAM console region. This allows having a
larger Pre-RAM console while not impacting the size of the PSP verstage
console.
Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in
`setup_cbmem_console`, I chose to use the offsets provided in the
transfer buffer. It would be nice to eventually do this for all the
fields in the transfer buffer.
BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are no longer truncated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block/cpu')
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 13 |
2 files changed, 16 insertions, 5 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc index 896512a0cd..461d3ee681 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc @@ -12,7 +12,13 @@ #endif ALIGN_COUNTER(64) - PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +#if ENV_SEPARATE_VERSTAGE + PRERAM_CBMEM_CONSOLE(., CONFIG_PRE_X86_CBMEM_CONSOLE_SIZE) +#else + REGION(cbmemc_transfer, ., CONFIG_PRE_X86_CBMEM_CONSOLE_SIZE, 4) +#endif /* ENV_SEPARATE_VERSTAGE */ +#endif /* CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) */ TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) FMAP_CACHE(., FMAP_SIZE) diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index e42174f765..88a8a60488 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -27,6 +27,9 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; * | | * | cbfs_cache (if reqd) | * | (CBFS_CACHE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | * +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE * | | * | verstage (if reqd) | @@ -48,11 +51,11 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; * | FMAP cache (FMAP_SIZE) | * +--------------------------------+ * | CBFS mcache (CBFS_MCACHE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRE_X86_CBMEM_CONSOLE_SIZE + 0x200 * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRE_X86_CBMEM_CONSOLE_SIZE + * | PSP Verstage CBMEM console | + * | (PRE_X86_CBMEM_CONSOLE_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE * | PSP shared (vboot workbuf) | * |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) | @@ -99,6 +102,8 @@ SECTIONS VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif + PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) + #if CONFIG_CBFS_CACHE_SIZE > 0 . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); CBFS_CACHE(., CONFIG_CBFS_CACHE_SIZE) |