diff options
| author | Martin Roth <gaumless@gmail.com> | 2022-11-20 20:30:18 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-24 15:16:45 +0000 |
| commit | 8180427a16ce0ae3138a6d3204ddd15ebd8142b3 (patch) | |
| tree | 2f9072ed048a4aeefe30cd2c6b2b682cc4454059 /src/soc/amd/common/block/cpu/car | |
| parent | 5e3798ca484b48843662c84967cc6ac88fa789dd (diff) | |
soc/amd: Define post codes
For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.
picasso/romstage.c did get a couple of post codes removed to match the
other files.
The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.
Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common/block/cpu/car')
| -rw-r--r-- | src/soc/amd/common/block/cpu/car/cache_as_ram.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 251e23aaad..b38ce80895 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -8,6 +8,7 @@ ****************************************************************************** */ +#include <amdblocks/post_codes.h> #include <cpu/x86/post_code.h> .section .init @@ -27,7 +28,7 @@ _cache_as_ram_setup: .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) AMD_ENABLE_STACK @@ -41,7 +42,7 @@ bootblock_pre_c_entry: pushl %eax /* tsc[31:0] */ before_carstage: - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry /* Never reached */ |