diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-11-24 14:16:34 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-04 12:23:50 +0000 |
| commit | 73a544d4533fa8305f1c0a809137b5e2151ea17e (patch) | |
| tree | e7d0b63098c2d021b579599a9ce419d3ced9db52 /src/soc/amd/common/block/acpimmio | |
| parent | c08fdf3decc6a61a9020a7df484d92473f7223e9 (diff) | |
soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable function
According to BKDGs for families 15h 60-6fh or newer and families 16h the
ACPI MMIO decode enable bit is the second LSB, not the first LSB.
Additionally create another enable function for older families where
the register and bit is different.
It does not seem to impact any current board, but may be crucial for
incoming C bootblock implementations when this bit will need to be set
very early. Most likely this bit is set by AGESA right now.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/acpimmio')
| -rw-r--r-- | src/soc/amd/common/block/acpimmio/mmio_util.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 04d5e4af4d..a589ef549a 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -18,13 +18,22 @@ #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> -void enable_acpimmio_decode(void) +void enable_acpimmio_decode_pm24(void) { uint32_t dw; - dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER); - dw |= ACPIMMIO_DECODE_EN; - pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw); + dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER_24); + dw |= PM_24_ACPIMMIO_DECODE_EN; + pm_io_write32(ACPIMMIO_DECODE_REGISTER_24, dw); +} + +void enable_acpimmio_decode_pm04(void) +{ + uint32_t dw; + + dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER_04); + dw |= PM_04_ACPIMMIO_DECODE_EN; + pm_io_write32(ACPIMMIO_DECODE_REGISTER_04, dw); } /* PM registers are accessed a byte at a time via CD6/CD7 */ |