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authorTim Van Patten <timvp@google.com>2022-08-16 12:09:23 -0600
committerMartin L Roth <gaumless@gmail.com>2022-09-19 09:53:17 +0000
commita90aebbf2a471b901bd1aa40e12e4f6a021b8ecc (patch)
treebc89fd3e4af2ac4b9c2ec2a0eba6892268e8c2c1 /src/soc/amd/common/acpi/dptc.asl
parent2d9e96a5ab175e126929e8d2314227cdd441857f (diff)
soc/amd/acpi: Add low/no battery mode to DPTC
Update acpigen_write_alib_dptc() to support "low/no battery mode", which throttles the SOC when there is no battery connected or the battery charge is critically low. This is in preparation for enabling this functionality for Mendocino. BUG=b:217911928 TEST=Build zork TEST=Boot nipperkin TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66804 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/acpi/dptc.asl')
-rw-r--r--src/soc/amd/common/acpi/dptc.asl12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/common/acpi/dptc.asl b/src/soc/amd/common/acpi/dptc.asl
index 611024cb02..e97aade50c 100644
--- a/src/soc/amd/common/acpi/dptc.asl
+++ b/src/soc/amd/common/acpi/dptc.asl
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
External(\_SB.DDEF, MethodObj)
+External(\_SB.DTHL, MethodObj)
External(\_SB.DTAB, MethodObj)
Scope (\_SB)
@@ -13,6 +14,17 @@ Scope (\_SB)
Return (Zero)
}
+ /* If _SB.DTHL is not present, then DPTC Tablet Mode is not enabled.
+ * Throttle the SOC if the battery is not present (BTEX), the battery level is critical
+ * (BFCR), or the battery is cutoff (BFCT). */
+ If (CondRefOf (\_SB.DTHL) &&
+ (!\_SB.PCI0.LPCB.EC0.BTEX || \_SB.PCI0.LPCB.EC0.BFCR || \_SB.PCI0.LPCB.EC0.BFCT))
+ {
+ \_SB.DTHL()
+ Return (Zero)
+ }
+
+ /* If _SB.DTAB is not present, then DPTC Tablet Mode is not enabled. */
If (CondRefOf (\_SB.DTAB) && (\_SB.PCI0.LPCB.EC0.TBMD == One))
{
\_SB.DTAB()