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authorFelix Held <felix-coreboot@felixheld.de>2023-05-10 15:07:47 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-06-06 17:28:29 +0000
commitd0959dc800657efea4906ea5509a41ac3ca6d99a (patch)
treeed5b015ac47117eed810b7d3c2c7408e9ac0a995 /src/soc/amd/cezanne
parent542abc1f493034b1d7ee8f4c3e1ddc5703c30016 (diff)
soc/amd/*/root_complex: reserve PCI config IO ports
This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne')
-rw-r--r--src/soc/amd/cezanne/root_complex.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index 6bef915085..a4134ef699 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -115,6 +115,8 @@ static void read_resources(struct device *dev)
/* The root complex has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */
+ fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
+
/* 0x0 - 0x9ffff */
ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);