soc/amd/cezanne: add verstage files

Add support for psp_verstage compilation.

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

6 files changed, 264 insertions, 1 deletions

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index f5cbcaebd0..e51a6163a8 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -5,6 +5,8 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
 
+subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
+
 # Beware that all-y also adds the compilation unit to verstage on PSP
 all-y		+= config.c
 all-y		+= aoac.c
@@ -130,6 +132,18 @@ PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | a
 APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h)
 APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h)
 
+ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
+# type = 0x6B - PSP Shared memory location
+ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0)
+PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE)
+PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map)
+endif
+
+# type = 0x52 - PSP Bootloader Userspace Application (verstage)
+PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
+PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN))
+endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK
+
 # Helper function to return a value with given bit set
 # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions.
 set-bit=$(call int-shift-left, 1 $(call _toint,$1))
@@ -143,6 +157,9 @@ PSP_SOFTFUSE=$(shell A=$(call int-add, \
 
 add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
 
+OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage)
+OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig)
+
 OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
                     $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
                     $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
@@ -152,6 +169,8 @@ OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
 OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
 OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
 
+OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem)
+OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size)
 OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size)
 OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base)
 OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
@@ -178,6 +197,8 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		--combo-capable \
 		$(OPT_TOKEN_UNLOCK) \
 		$(OPT_WHITELIST_FILE) \
+		$(OPT_PSP_SHAREDMEM_BASE) \
+		$(OPT_PSP_SHAREDMEM_SIZE) \
 		$(OPT_EFS_SPI_READ_MODE) \
 		$(OPT_EFS_SPI_SPEED) \
 		$(OPT_EFS_SPI_MICRON_FLAG) \
@@ -186,10 +207,13 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		--flashsize $(CONFIG_ROM_SIZE)
 
 $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
+			$(PSP_VERSTAGE_FILE) \
+			$(PSP_VERSTAGE_SIG_FILE) \
 			$$(PSP_APCB_FILES) \
 			$(DEP_FILES) \
 			$(AMDFWTOOL) \
-			$(obj)/fmap_config.h
+			$(obj)/fmap_config.h \
+			$(objcbfs)/bootblock.elf # this target also creates the .map file
 	$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
 	rm -f $@
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
@@ -197,6 +221,8 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 		$(AMDFW_COMMON_ARGS) \
 		$(OPT_APOB_NV_SIZE) \
 		$(OPT_APOB_NV_BASE) \
+		$(OPT_VERSTAGE_FILE) \
+		$(OPT_VERSTAGE_SIG_FILE) \
 		--location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \
 		--multilevel \
 		--output $@
diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
new file mode 100644
index 0000000000..bdc46cb84e
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_PSP_VERSTAGE_ADDR_H
+#define AMD_CEZANNE_PSP_VERSTAGE_ADDR_H
+
+/*
+ * Start of available space is 0x36000 and this is where the
+ * header for the user app (verstage) must be mapped.
+ * Size is 0x14000 bytes
+ */
+#define PSP_SRAM_START			0x36000
+#define PSP_SRAM_SIZE			(80K)
+#define VERSTAGE_START			PSP_SRAM_START
+
+/*
+ * The top of the stack must be 4k aligned, so set the bottom as 4k aligned
+ * and make the size a multiple of 4k
+ */
+
+#define PSP_VERSTAGE_STACK_START	0x49000
+#define PSP_VERSTAGE_STACK_SIZE		(4K)
+
+#endif  /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */
diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc
new file mode 100644
index 0000000000..8f268ca57d
--- /dev/null
+++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+verstage-generic-ccopts += -I$(src)/soc/amd/cezanne/psp_verstage/include
+verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/cezanne/include
+
+verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
+
+subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
+
+verstage-y += svc.c
+verstage-y += stub.c
+
+verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S
+verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S
+
+$(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf
+	$(OBJCOPY_verstage) -O binary $^ $@
diff --git a/src/soc/amd/cezanne/psp_verstage/stub.c b/src/soc/amd/cezanne/psp_verstage/stub.c
new file mode 100644
index 0000000000..b3ec7044b4
--- /dev/null
+++ b/src/soc/amd/cezanne/psp_verstage/stub.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This file contains stub for not-yet-implemented svc in cezanne PSP.
+ * So this file will and should be removed eventually when psp_verstage works
+ * correctly in cezanne.
+ */
+
+#include <bl_uapp/bl_syscall_public.h>
+#include <console/console.h>
+#include <psp_verstage.h>
+#include <reset.h>
+#include <timer.h>
+
+uint32_t svc_write_postcode(uint32_t postcode)
+{
+	return 0;
+}
+
+static uint64_t tmp_timer_value = 0;
+void timer_monotonic_get(struct mono_time *mt)
+{
+	mt->microseconds = tmp_timer_value / 1000;
+	tmp_timer_value++;
+}
+
+void do_board_reset(void)
+{
+	printk(BIOS_ERR, "Reset not implemented yet.\n");
+	while (1)
+		;
+}
diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c
new file mode 100644
index 0000000000..3d10c22663
--- /dev/null
+++ b/src/soc/amd/cezanne/psp_verstage/svc.c
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "svc.h"
+
+#include <assert.h>
+#include <bl_uapp/bl_syscall_public.h>
+#include <psp_verstage.h>
+#include <stddef.h>
+
+void svc_exit(uint32_t status)
+{
+	uint32_t unused = 0;
+	SVC_CALL0(SVC_EXIT, unused);
+}
+
+void svc_debug_print(const char *string)
+{
+	uint32_t unused = 0;
+	SVC_CALL1(SVC_DEBUG_PRINT, (uint32_t)string, unused);
+}
+
+void svc_debug_print_ex(uint32_t dword0,
+		uint32_t dword1, uint32_t dword2, uint32_t dword3)
+{
+	uint32_t unused = 0;
+	SVC_CALL4(SVC_DEBUG_PRINT_EX, dword0, dword1, dword2, dword3, unused);
+}
+
+uint32_t svc_get_boot_mode(uint32_t *boot_mode)
+{
+	uint32_t retval = 0;
+	SVC_CALL1(SVC_GET_BOOT_MODE, boot_mode, retval);
+	return retval;
+}
+
+void svc_delay_in_usec(uint32_t delay)
+{
+	uint32_t i;
+	for (i = 0; i < delay * 1000; i++)
+		asm volatile ("nop");
+}
+
+uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info)
+{
+	uint32_t retval = 0;
+	SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval);
+	return retval;
+}
+
+uint32_t svc_map_fch_dev(enum fch_io_device io_device,
+		uint32_t arg1, uint32_t arg2, void **io_device_axi_addr)
+{
+	uint32_t retval = 0;
+	assert(io_device < FCH_IO_DEVICE_END);
+	SVC_CALL4(SVC_MAP_FCH_IO_DEVICE, io_device, arg1, arg2,
+			(uint32_t)io_device_axi_addr, retval);
+	return retval;
+}
+
+uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr)
+{
+	uint32_t retval = 0;
+	assert(io_device < FCH_IO_DEVICE_END);
+	SVC_CALL2(SVC_UNMAP_FCH_IO_DEVICE, (uint32_t)io_device,
+			(uint32_t)io_device_axi_addr, retval);
+	return retval;
+}
+
+uint32_t svc_map_spi_rom(void *spi_rom_addr,
+		uint32_t size, void **spi_rom_axi_addr)
+{
+	uint32_t retval = 0;
+	SVC_CALL3(SVC_MAP_SPIROM_DEVICE, spi_rom_addr, size,
+			(uint32_t)spi_rom_axi_addr, retval);
+	return retval;
+}
+
+uint32_t svc_unmap_spi_rom(void *spi_rom_addr)
+{
+	uint32_t retval = 0;
+	SVC_CALL1(SVC_UNMAP_SPIROM_DEVICE, (uint32_t)spi_rom_addr, retval);
+	return retval;
+}
+
+uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset)
+{
+	return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset);
+}
+
+uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset,
+		uint32_t *bios_dir_offset)
+{
+	uint32_t retval = 0;
+	SVC_CALL2(SVC_UPDATE_PSP_BIOS_DIR, (uint32_t)psp_dir_offset,
+			(uint32_t)bios_dir_offset, retval);
+	return retval;
+}
+
+uint32_t save_uapp_data(void *address, uint32_t size)
+{
+	return svc_save_uapp_data(address, size);
+}
+
+uint32_t svc_save_uapp_data(void *address, uint32_t size)
+{
+	uint32_t retval = 0;
+	SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval);
+	return retval;
+}
diff --git a/src/soc/amd/cezanne/psp_verstage/svc.h b/src/soc/amd/cezanne/psp_verstage/svc.h
new file mode 100644
index 0000000000..e44948e04b
--- /dev/null
+++ b/src/soc/amd/cezanne/psp_verstage/svc.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef PSP_VERSTAGE_SVC_H
+#define PSP_VERSTAGE_SVC_H
+
+#define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \
+	__asm__ __volatile__ ( \
+	"mov r0, %[reg0]\n\t" \
+	"mov r1, %[reg1]\n\t" \
+	"mov r2, %[reg2]\n\t" \
+	"mov r3, %[reg3]\n\t" \
+	"svc %[id]\n\t" \
+	"mov %[result], r0\n\t" \
+	: [result] "=r" (Ret) /* output */ \
+	: [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2), \
+		[reg3] "r" (R3) /* input(s) */ \
+	: "r0", "r1", "r2", "r3", "memory", "cc" /* list of clobbered registers */)
+
+#define SVC_CALL3(SVC_ID, R0,  R1, R2, Ret) \
+	__asm__ __volatile__ ( \
+	"mov r0, %[reg0]\n\t" \
+	"mov r1, %[reg1]\n\t" \
+	"mov r2, %[reg2]\n\t" \
+	"svc %[id]\n\t" \
+	"mov %[result], r0\n\t" \
+	: [result] "=r" (Ret) /* output */ \
+	: [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2) \
+	: "r0", "r1", "r2", "memory", "cc" /* list of clobbered registers */)
+
+#define SVC_CALL2(SVC_ID, R0, R1, Ret) \
+	__asm__ __volatile__ ( \
+	"mov r0, %[reg0]\n\t" \
+	"mov r1, %[reg1]\n\t" \
+	"svc %[id]\n\t" \
+	"mov %[result], r0\n\t" \
+	: [result] "=r" (Ret) /* output */ \
+	: [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1)/* input(s) */ \
+	: "r0", "r1", "memory", "cc" /* list of clobbered registers */)
+
+#define SVC_CALL1(SVC_ID, R0, Ret) \
+	__asm__ __volatile__ ( \
+	"mov r0, %[reg0]\n\t" \
+	"svc %[id]\n\t" \
+	"mov %[result], r0\n\t" \
+	: [result] "=r" (Ret) /* output */ \
+	: [id] "i" (SVC_ID), [reg0] "r" (R0) /* input(s) */ \
+	: "r0", "memory", "cc" /* list of clobbered registers */)
+
+#define SVC_CALL0(SVC_ID, Ret) \
+	__asm__ __volatile__ ( \
+	"svc %[id]\n\t" \
+	"mov %[result], r0\n\t" \
+	: [result] "=r" (Ret) /* output */ \
+	: [id] "I" (SVC_ID) /* input(s) */ \
+	: "memory", "cc" /* list of clobbered registers */)
+
+#endif /* PSP_VERSTAGE_SVC_H */