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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-26 09:32:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-01 08:27:14 +0000 |
| commit | a8f76904fbd2edf09807ee21afeae0fea8510d7f (patch) | |
| tree | c47e7c4f241d22a7a389e92d0232ed48a2416552 /src/soc/amd/cezanne | |
| parent | d40a4c2bb4d237c174ef11ad73afc5a67ed555e7 (diff) | |
nb/intel/haswell: Fix DPR size handling
DPR register's size field is given in whole MiB, so correct where it is
used to ensure the correct size multiple (KiB vs. MiB) is used with it.
Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling")
Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne')
0 files changed, 0 insertions, 0 deletions