diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-31 21:25:53 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-14 12:49:00 +0000 |
| commit | a19bc34430200f34286f3ba5e8b1df569b69fe8b (patch) | |
| tree | 631163ccf6815afa37750a17e7330eb994023555 /src/soc/amd/cezanne | |
| parent | 7f611018d4bc7b5eda2ecfa3d8bff4dedf832d52 (diff) | |
soc/amd/*: Move apm call out of MP init code
This makes it easier to have common code for MP init on AMD systems.
Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/cpu.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index ada0e92fab..a22b369024 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -40,21 +40,12 @@ static void pre_mp_init(void) x86_mtrr_check(); } -static void post_mp_init(void) -{ - global_smi_enable(); - - /* SMMINFO only needs to be set up when booting from S5 */ - if (!acpi_is_wakeup_s3()) - apm_control(APM_CNT_SMMINFO); -} - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, + .post_mp_init = global_smi_enable, }; void mp_init_cpus(struct bus *cpu_bus) @@ -65,6 +56,10 @@ void mp_init_cpus(struct bus *cpu_bus) /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); } static void zen_2_3_init(struct device *dev) |