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authorFelix Held <felix.held@amd.corp-partner.google.com>2021-08-30 18:20:34 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-08-15 15:33:52 +0000
commit8db77d71bbbb872831a6bb61dac249d551773a84 (patch)
tree88fc6554faca16253bc7d9869ca1694d5b824cb2 /src/soc/amd/cezanne
parentb02cc14367890661ca047ffe8c5d86a3e6bac95d (diff)
soc/amd/*: move reset_i2c_peripherals call after early GPIO setup
Since bootblock_soc_early_init gets called before bootblock_mainboard_early_init which does the early GPIO setup, external I2C level shifters that are controlled by GPIOs might not be enabled yet. Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure that the early GPIO setup is already done when reset_i2c_peripherals is called. Haven't probed any SCL signal on the non-SoC side of the I2C level shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a barla/careena Chromebook doesn't have the longer than expected SCL pulses any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne')
-rw-r--r--src/soc/amd/cezanne/early_fch.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 027a0b54bf..586e80cbd0 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -51,7 +51,6 @@ void fch_pre_init(void)
fch_enable_legacy_io();
fch_disable_legacy_dma_io();
enable_aoac_devices();
- reset_i2c_peripherals();
/*
* On reset Range_0 defaults to enabled. We want to start with a clean
@@ -70,6 +69,7 @@ void fch_pre_init(void)
/* After console init */
void fch_early_init(void)
{
+ reset_i2c_peripherals();
pm_set_power_failure_state();
fch_print_pmxc0_status();
i2c_soc_early_init();