diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-07-16 13:53:29 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-07-19 14:58:53 +0000 |
| commit | 73193cf7b77592d52bb0c60da887af227ac0ace7 (patch) | |
| tree | d0cf340da2b0f165dc80fc3fd0faad2ecf52e51d /src/soc/amd/cezanne | |
| parent | f72568cad31092df5c3bc7a87536b84ab178cfa7 (diff) | |
soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE
This change allows preloading the payload.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We
now spend 7ms decompression from RAM. By switching to LZ4 we drop that
to 500us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fsp_s_params.c | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 5da70f4e0b..b58e45398e 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -31,6 +31,7 @@ config SOC_SPECIFIC_OPTIONS select IDT_IN_EVERY_STAGE select IOAPIC select PARALLEL_MP_AP_WORK + select PAYLOAD_PRELOAD select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select RESET_VECTOR_IN_RAM diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index 96dc61bf80..60f3942802 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <amdblocks/apob_cache.h> #include <device/pci.h> #include <fsp/api.h> +#include <program_loading.h> static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { @@ -22,4 +24,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * no SPI operations, we can read the APOB while FSP-S executes. */ start_apob_cache_read(); + /* + * We enqueue the payload to be loaded after the APOB. This might cause a bit of + * bus contention when loading uCode and OPROMs, but since those calls happen at + * different points in the boot state machine it's a little harder to sequence all the + * async loading correctly. So in order to keep the complexity down, we enqueue the + * payload preload here. The end goal will be to add uCode and OPROM preloading + * before the payload so that the sequencing is correct. + * + * While FSP-S is executing, it's not currently possible to enqueue other transactions + * because FSP-S doesn't call `thread_yield()`. So the payload will start loading + * right after FSP-S completes. + */ + if (!acpi_is_wakeup_s3()) + payload_preload(); } |