diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-11-01 10:49:16 -0400 |
|---|---|---|
| committer | Fred Reitberger <reitbergerfred@gmail.com> | 2022-11-04 20:36:49 +0000 |
| commit | 2890841e6f8ff05850d2327480fda260020e5c61 (patch) | |
| tree | 34891f2624b77e6b936c1d6e5aa436938cb341e6 /src/soc/amd/cezanne | |
| parent | 437d011621cb3c1b929314c5807c2e3d014906d8 (diff) | |
soc/amd/*/data_fabric: Move register offsets to soc
Morgana/Glinda have a different register mapping for data fabric access,
although the registers themselves are mostly compatible. The register
layouts defined by each soc capture the differences and the common code
can use those.
Move the register offsets to soc headers and update the offsets for
morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254,
rev 1.51
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/data_fabric.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 0a89971198..a1f8b700c7 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -5,8 +5,15 @@ #include <types.h> -/* SoC-specific bits in D18F0_MMIO_CTRL0 */ -#define DF_MMIO_NP BIT(16) +/* D18F0 - Fabric Configuration registers */ +#define D18F0_MMIO_BASE0 0x200 +#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0x208 + +#define DF_FICAA_BIOS 0x5C +#define DF_FICAD_LO 0x98 +#define DF_FICAD_HI 0x9C #define IOMS0_FABRIC_ID 10 |