diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-10-17 11:49:55 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-18 16:09:44 +0000 |
| commit | 13831223bec0fada21a703fa23b06663942f11de (patch) | |
| tree | b6de37653ca1a965e7df16fbed4d88b72ec15fe6 /src/soc/amd/cezanne | |
| parent | f2b36036c7b2906071543a8c9590fdbb0f53dfc9 (diff) | |
soc/amd/*/i2c: Move reset_i2c_peripherals to i2c.c
Move i2c SoC related code from early_fch.c to i2c.c
TEST=build boards for each SoC
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/early_fch.c | 18 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/i2c.c | 19 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/i2c.h | 1 |
3 files changed, 20 insertions, 18 deletions
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 3addcf8c5d..4935f661db 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -12,13 +12,6 @@ #include "chip.h" -/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ -static const struct soc_i2c_scl_pin i2c_scl_pins[] = { - I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), - I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), - I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), - I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), -}; static void lpc_configure_decodes(void) { @@ -26,17 +19,6 @@ static void lpc_configure_decodes(void) lpc_enable_port80(); } -static void reset_i2c_peripherals(void) -{ - const struct soc_amd_cezanne_config *cfg = config_of_soc(); - struct soc_i2c_peripheral_reset_info reset_info; - - reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; - reset_info.i2c_scl = i2c_scl_pins; - reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); - sb_reset_i2c_peripherals(&reset_info); -} - /* Before console init */ void fch_pre_init(void) { diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c index ae49a064e0..98e2413ee9 100644 --- a/src/soc/amd/cezanne/i2c.c +++ b/src/soc/amd/cezanne/i2c.c @@ -6,6 +6,14 @@ #include <soc/southbridge.h> #include "chip.h" +/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), +}; + #if ENV_X86 static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" }, @@ -32,6 +40,17 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) } #endif +void reset_i2c_peripherals(void) +{ + const struct soc_amd_cezanne_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { const struct soc_amd_cezanne_config *config = config_of_soc(); diff --git a/src/soc/amd/cezanne/include/soc/i2c.h b/src/soc/amd/cezanne/include/soc/i2c.h index dba16db2db..c0e3e800bb 100644 --- a/src/soc/amd/cezanne/include/soc/i2c.h +++ b/src/soc/amd/cezanne/include/soc/i2c.h @@ -24,5 +24,6 @@ #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx void i2c_set_bar(unsigned int bus, uintptr_t bar); +void reset_i2c_peripherals(void); #endif /* AMD_CEZANNE_I2C_H */ |